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基于ISA总线的纳秒级同步器的研制 被引量:5

Develop on NS Synchroniser Based on ISA Bus
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摘要 基于 ISA 总线的纳秒级同步器采用可编程硬件延时设计,其电路采用 10 片 MC100E195 级联,17 位地址选择线通过并行接口 8255 控制门电路。晶振脉冲分频后经 8254 计数并产生基准信号,送可编程门阵列 MC100E195,得到 20ns 级的延迟范围。采用 VC++ 对同步器硬件端口操作,通过参数设置,得到多路延时同步信号。 The ns synchronizer based on ISA bus was designed with programmable hardware delay, ns hardware circuit were connected with cascade connection of 10 pieces of MC100E195, and gate circuit was controlled by 17 bit addresses choosing bus through parallel interface 8255. It makes 8254 generate a vibratory pulse and this pulse triggers a gate arrays to generate a 20 ns grade delay pulse. 20 ns grade delay pulse was sent into MC100E195, delay range of 20 ns grade was gained. The operation of synchroniser hardware port was implemented with VC++, and multi-path delay synchronization signal was gained by setting parameter.
出处 《兵工自动化》 2004年第6期72-73,共2页 Ordnance Industry Automation
关键词 同步器 纳秒级 可编程硬件延时 ISA总线 Synchroniser NS (nanosecond) Programmable hardware delay ISA bus
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参考文献2

  • 1[1]周明德.微型计算机系统原理及应用(第三版)[M].北京:清华大学出版社,1999.
  • 2[2]邹逢芳.计算机硬件技术基础[M].北京:高等教育出版社,1999.

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