摘要
为满足低压、高速、低耗数字系统的应用需求 ,通过采用改进电路结构和优化器件参数的方法 ,设计了三种改进结构型BiCMOS逻辑单元电路。实验结果表明 ,所设计电路不但具有确定的逻辑功能 ,而且获得了高速、低压、低耗和接近于全摆幅的特性 ,它们的工作速度比高速CMOS和原有的互补对称BiCMOS(CBiCMOS)电路快约一倍 ,功耗在 6 0MHz频率下仅高出 1 4 9～ 1 71mW ,但延迟 功耗积却比原CBiCMOS电路平均降低了4 0 3%。
To meet the application needs of low-voltage, high-speed and low-consumption digital system, 3 kinds of high performance BiCMOS logic units were designed by means of modifying structure and using optimal parameters. The related analysis, simulation and the result of the experiment have shown that the logic function of them can be confirmed and their high performance can be obtained in terms of speed, output voltage swing and power consumption. As a result, their speed even reaches about 2 times of those of CMOS and conventional CBiCMOS units, their power consumption is only over 1 49～1 71 mW at 60 MHz, but their delay-consumption product is reduced by an average of 40 3% compared with conventional CBiCMOS accordingly.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2004年第4期486-492,共7页
Research & Progress of SSE
基金
江苏省高校自然科学研究基金项目 (编号 :0 2KJB5 10 0 0 5 )
