摘要
传统的微控制器(MCU)通常采用串行菊花链中断结构,每次都要按照优先级顺序串行查询中断源,在中断源比较多或需要快速实时处理的场合,无法满足中断响应时间的要求。文章在介绍两优先级11个可屏蔽中断源的中断系统基础上,提出了一种并行优先级中断结构,给出了详细的硬件描述语言实现流程图。该中断系统嵌入到所设计的高速MCU核里,通过Altera的APEX20KEFPGA开发板引出MCU的端口引脚,在实际微控制器应用系统上成功地进行了测试。
Traditional Micro-Controller Unit (MCU) usually uses daisy chain interrupt hardware. It is much a waste of time that MCU polls interrupt sources according to their orders of priority each time. Based on a multi-level interrupt system with two priorities and eleven maskable interrupts, a parallel priority interrupt hardware, illustrated with program flow chart, is proposed. Embedded in a fast 8051 compatible MCU core, the interrupt system is verified by stretching port pins of MCU core from FPGA development board of Altera APEX20KE into various microcontroller application systems.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第4期482-485,共4页
Microelectronics
基金
上海市教委自然科学项目(03AK16)
上海市科委技术攻关项目(025911323)资助
