摘要
非易失性存储器应用在存储测试中具有存储容量大,掉电后数据不丢失的优点。在存储测试系统中,为了能完整地记录测试信号,在电路中使用负延时来记录电路触发点以前的数据。负延时功能在触发信号为被测信号的幅值达到触发阈值触发电路时,显得更加重要。本文介绍了使用单片机结合CPLD控制两片NAND结构闪存实现高速存储,并实现负延时功能。本装置实现了小体积,微功耗,高过载。
Flash memory which was used in stored testing and measuring system provides mass storage and keep data while electrical source exhaust. Negative delay time is adopted to record the signal before the trigger point. It is important when testing signal as threshold to trigger recording. This article introduces CPLD unite MCU controlling two NAND flash memories high speed storage of data. This device is small size, low power consumption, high over loading resistance.
出处
《仪器仪表学报》
EI
CAS
CSCD
北大核心
2006年第z2期1517-1518,共2页
Chinese Journal of Scientific Instrument
关键词
负延时
存储测试
NAND闪存
negative delay time stored testing NAND flash memory
