FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other typ...FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of DNN.For ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC operation.The other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of DNN.For memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/5.Other designs are new architecture and specialized AI engine.Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform.Its AI engine can provide up to 8X silicon compute density.Intel AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.展开更多
Resistive switching characteristics of CuxO films grown by plasma oxidation process at room temperature are investigated. Both bipolar and unipolar stable resistive switching behaviours are observed and confirmed by r...Resistive switching characteristics of CuxO films grown by plasma oxidation process at room temperature are investigated. Both bipolar and unipolar stable resistive switching behaviours are observed and confirmed by repeated current voltage measurements. It is found that the RESET current is dependent on SET compliance current. The mechanism behind this new phenomenon can be understood in terms of conductive filaments formation/rupture with the contribution of Joule heating.展开更多
Thermal stability of resistive switching of stoichiometric zirconium oxide thin films is investigated for high yielding nonvolatile memory application. The A1/ZrO2/AI cell fabricated in the conventional device process...Thermal stability of resistive switching of stoichiometric zirconium oxide thin films is investigated for high yielding nonvolatile memory application. The A1/ZrO2/AI cell fabricated in the conventional device process shows highly reliable switching behaviour between two distinct stable resistance states. The retention capabilities are also tested under various conditions and temperatures. The excellent performance of Ai/ZrO2/AI ceil can be explained by assuming that anode/ZrO2 interface exists and by conducting filament forming/rupture mechanism. The device failure is illustrated in terms of permanent conducting filaments formation.展开更多
Ultrafast third-order optical nonlinearities of the as-deposited and annealed Au：Bi2O3 nanocomposite films deposited by magnetron cosputtering are investigated by using femtosecond time-resolved optical Kerr effect ...Ultrafast third-order optical nonlinearities of the as-deposited and annealed Au：Bi2O3 nanocomposite films deposited by magnetron cosputtering are investigated by using femtosecond time-resolved optical Kerr effect （OKE） and pump probe techniques. The third-order optical nonlinear susceptibility is estimated to be 2.6Ф×10^- 10 esu and 1.8 × 10.9 esu at wavelength of 800nm, for the as-deposited and the annealed film, respectively. The OKE signal of the as-deposited film is nearly temporally symmetrical with a peak centred at zero delay time, which indicates the dominant contribution from intraband transition of conduction electrons. For the annealed film, the existence of a decay process in OKE signal implies the important contribution of hot electrons. These characteristics are in agreement with the hot electron dynamics observed in pump probe measurement.展开更多
Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it...Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing (SA) converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route (VPR) Tool.展开更多
An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the...An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.展开更多
An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage ...An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.展开更多
Currently,digital certificate systems based on blockchain have been extensively developed and adopted.However,most of them do not take into account the certificate quality.To evaluate the credibility of certificates i...Currently,digital certificate systems based on blockchain have been extensively developed and adopted.However,most of them do not take into account the certificate quality.To evaluate the credibility of certificates issued by educational institutions,we propose a novel blockchain-based system with credit self-adjustment(BC-CS).In BC-CS,employers can provide feedback according to the performances of their employees(i.e.,students)holding different certificates.Based on the feedback,BC-CS automatically adjusts the certificate credits by using our proposed credit self-adjustment algorithm.To verify the feasibility of our proposed system,a decentralized application prototype has been developed on an Ethereum network.Experimental results demonstrate that the proposed system can fully support multistep accreditation and automatic adjustment for certificate credit.展开更多
A novel scheme to generate, transmit, and receive an optical orthogonal frequency division multiplexing （OFDM） continuous phase modulation （CPM） signal, which is combining minimum shift keying （MSK） coding with ...A novel scheme to generate, transmit, and receive an optical orthogonal frequency division multiplexing （OFDM） continuous phase modulation （CPM） signal, which is combining minimum shift keying （MSK） coding with OFDM optical modulation, for downlink application in a 4×2.5-Gb/s wavelength division multiplexing （WDM） passive optical access network, is proposed and experimentally validated. We also realize wavelength remodulation for carrying upstream on-off keying （OOK） data to reduce the cost budget at the optical network unit. The experimental results show that the power penalties for the downlink and the uplink data after transmission over 25-km SMF-28 fiber are 0.1 dB and smaller than 0.4 dB, respectively.展开更多
A novel 40-Gb/s constant envelope optical frequency shift keying （FSK） transmitter and the transmission characteristics are investigated both by simulation and experiment. Meanwhile, to increase the spectrum efficie...A novel 40-Gb/s constant envelope optical frequency shift keying （FSK） transmitter and the transmission characteristics are investigated both by simulation and experiment. Meanwhile, to increase the spectrum efficiency of FSK, we propose a novel optical minimum-shift keying （MSK） scheme and analyze its per-formance compared with other MSK schemes and other traditional modulation formats. Simulation and experimental results show that the novel FSK scheme could be a potential candidate for the future high speed transmission and label switching systems. And the novel MSK scheme deserves future deep research for its potential excellent performance.展开更多
A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of fr...A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.展开更多
We experimentally demonstrate a 4-Gb/s radio-over-fiber （RoF） system with 40-kin fiber and 2-m wireless distance downstream at 100-GHz carrier. To the best of our knowledge, this is for the first time in China to re...We experimentally demonstrate a 4-Gb/s radio-over-fiber （RoF） system with 40-kin fiber and 2-m wireless distance downstream at 100-GHz carrier. To the best of our knowledge, this is for the first time in China to realize optical wireless link at 100 GHz. In this letter, simple intensity modulator with direct detector （IM-DD） modulation is employed and optical power penalty afZer 40-kin single mode fiber （SMF）-28 and 2-m air link is 3.2 dB with bit-error-rate （BER） at 1 × 10- 9.展开更多
With the rapid development of the light-emitting diode （LED） industry, interest in visible light communication （VLC） is growing. The limited bandwidth of commercial LEDs is one of the main challenges to achieve hi...With the rapid development of the light-emitting diode （LED） industry, interest in visible light communication （VLC） is growing. The limited bandwidth of commercial LEDs is one of the main challenges to achieve high- speed VLC. In this Letter, a kind of bandwidth-efficient VLC system based on carrierless amplitude and phase （CAP） modulation is proposed, where a simple differential faster-than-Nyquist （FTN） pre-coding scheme is em- ployed to compress the spectrum and further improve the overall system baud rate. The system is experimentally demonstrated with a data rate of 1.47-Cb/s over 1.5 m free space transmission. The results indicate that an improvement of 80 Mbaud is achieved by FTN-CAP4 at 20% subband overlap and 40 Mbaud rate improvement by FTN-CAP16 at 7.5% subband overlap. Compared with traditional CAP, the FTN pre-coded CAP shows a better performance in spectral efficiency （SE） and intercarrier interference resistance. To the best of our knowl- edge, it is the first time to employ FTN pre-coded CAP in indoor high-data-rate VLC systems.展开更多
In this Letter, we propose a novel constellation-shaping carrier-less amplitude and phase （CAP） modulation scheme to alleviate the systematic nonlinearity in visible light communication （VLC） systems. A simple geo...In this Letter, we propose a novel constellation-shaping carrier-less amplitude and phase （CAP） modulation scheme to alleviate the systematic nonlinearity in visible light communication （VLC） systems. A simple geo- metric transformation shaping method is employed to convert the normal square lattice constellation into multi- ple circular constellations. The feasibility and performance are investigated and experimentally demonstrated by a 1.25 Gb/s CAP-modulated VLC system. The results indicate that the circular constellation has better resis- tance to systematic nonlinearity compared with a rectangular constellation. The dynamic range of input signal peak-to-peak values promotes 20% at a low bias voltage nonlinear area and 50% at a high bias voltage nonlinear area. To the best of our knowledge, this is the first time constellation-shaping CAP has ever been reported in indoor high data rate VLC systems.展开更多
We propose a novel advanced orthogonal modulation format dark return-to-zero frequency shift keying/differential phase shift keying （DRZ-FSK/DPSK） and its realization scheme. The DRZ-FSK/DPSK is generated by the com...We propose a novel advanced orthogonal modulation format dark return-to-zero frequency shift keying/differential phase shift keying （DRZ-FSK/DPSK） and its realization scheme. The DRZ-FSK/DPSK is generated by the combination of a 40-Gb/s return-to-zero （RZ） signal and a DRZ signal which is converted from the RZ using a semiconductor optical amplifier （SOA） based on nonlinear cross polarization rotation （XPR） and then re-modulated by high-bit-rate DPSK at 40 Gb/s. The feasibility of the scheme is exper-imentally demonstrated. Bit error rate （BER） results of the total 80-Gb/s DRZ-FSK/DPSK orthogonal modulation signal with a subsequent 100-km single-mode fiber （SMF） transmission link show its potential for future high-speed long-haul optical communication.展开更多
We propose a reeonfigurable control-bit generation algorithm for rotation and sub-word rotation operations. The algorithm uses a self-routing characteristic to configure an inverse butterfly network. In addition to be...We propose a reeonfigurable control-bit generation algorithm for rotation and sub-word rotation operations. The algorithm uses a self-routing characteristic to configure an inverse butterfly network. In addition to being highly parallelized and inexpensive, the algorithm integrates the rotation-shift, bi-directional rotation-shift, and sub-word rotation-shift operations. To our best knowledge, this is the first scheme to accommodate a variety of rotation operations into the same architecture. We have developed the highly efficient reconfigurable rotation unit （HERRU） and synthesized it into the Semiconductor Manufacturing International Corporation （SMIC）＇s 65-nm process. The results show that the overall efficiency （relative areaxrelative latency） of our HERRU is higher by at least 23% than that of other designs with similar functions. When executing the bi-directional rotation operations alone, HERRU occupies a significantly smaller area with a lower latency than previously proposed designs.展开更多
RSA and ellipse curve cryptography(ECC)algorithms are widely used in authentication,data security,and access control.In this paper,we analyze the basic operation of the ECC and RSA algorithms and optimize their modula...RSA and ellipse curve cryptography(ECC)algorithms are widely used in authentication,data security,and access control.In this paper,we analyze the basic operation of the ECC and RSA algorithms and optimize their modular multiplication and modular inversion algorithms.We then propose a reconfigurable modular operation architecture,with a mix-memory unit and double multiply-accumulate structures,to realize our unified,asymmetric cryptosystem structure in an operational unit.Synthesized with 55-nm CMOS process,our design runs at 588 MHz and requires only 437801µm2 of hardware resources.Our proposed design takes 21.92 and 23.36 mW for 2048-bit RSA modular multiplication and modular inversion respectively,as well as 16.16 and 15.88 mW to complete 512-bit ECC dual-field modular multiplication and modular inversion respectively.It is more energy-efficient and flexible than existing single algorithm units.Compared with existing multiple algorithm units,our proposed method shows better performance.The operation unit is embedded in a 64-bit RISC-V processor,realizing key generation,encryption and decryption,and digital signature functions of both RSA and ECC.Our proposed design takes 0.224 and 0.153 ms for 256-bit ECC point multiplication in G(p)and G(2^(m))respectively,as well as 0.96 ms to complete 1024-bit RSA exponentiation,meeting the demand for high energy efficiency.展开更多
文摘FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of DNN.For ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC operation.The other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of DNN.For memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/5.Other designs are new architecture and specialized AI engine.Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform.Its AI engine can provide up to 8X silicon compute density.Intel AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.
基金Supported by the National Natural Science Foundation of China under Grant Nos 60706033 and 60676007.
文摘Resistive switching characteristics of CuxO films grown by plasma oxidation process at room temperature are investigated. Both bipolar and unipolar stable resistive switching behaviours are observed and confirmed by repeated current voltage measurements. It is found that the RESET current is dependent on SET compliance current. The mechanism behind this new phenomenon can be understood in terms of conductive filaments formation/rupture with the contribution of Joule heating.
基金Supported by the National Natural Science Foundation of China under Grant Nos 60706033, 60578047 and 60676007.
文摘Thermal stability of resistive switching of stoichiometric zirconium oxide thin films is investigated for high yielding nonvolatile memory application. The A1/ZrO2/AI cell fabricated in the conventional device process shows highly reliable switching behaviour between two distinct stable resistance states. The retention capabilities are also tested under various conditions and temperatures. The excellent performance of Ai/ZrO2/AI ceil can be explained by assuming that anode/ZrO2 interface exists and by conducting filament forming/rupture mechanism. The device failure is illustrated in terms of permanent conducting filaments formation.
基金Supported by the National Natural Science Foundation of China under Grant Nos 10374020 and 10674031.
文摘Ultrafast third-order optical nonlinearities of the as-deposited and annealed Au：Bi2O3 nanocomposite films deposited by magnetron cosputtering are investigated by using femtosecond time-resolved optical Kerr effect （OKE） and pump probe techniques. The third-order optical nonlinear susceptibility is estimated to be 2.6Ф×10^- 10 esu and 1.8 × 10.9 esu at wavelength of 800nm, for the as-deposited and the annealed film, respectively. The OKE signal of the as-deposited film is nearly temporally symmetrical with a peak centred at zero delay time, which indicates the dominant contribution from intraband transition of conduction electrons. For the annealed film, the existence of a decay process in OKE signal implies the important contribution of hot electrons. These characteristics are in agreement with the hot electron dynamics observed in pump probe measurement.
基金Supported by School of Engineering, Napier University, United Kingdom, and partially supported by the National Natural Science Foundation of China (No.60273093).
文摘Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing (SA) converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route (VPR) Tool.
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.
文摘An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.
文摘Currently,digital certificate systems based on blockchain have been extensively developed and adopted.However,most of them do not take into account the certificate quality.To evaluate the credibility of certificates issued by educational institutions,we propose a novel blockchain-based system with credit self-adjustment(BC-CS).In BC-CS,employers can provide feedback according to the performances of their employees(i.e.,students)holding different certificates.Based on the feedback,BC-CS automatically adjusts the certificate credits by using our proposed credit self-adjustment algorithm.To verify the feasibility of our proposed system,a decentralized application prototype has been developed on an Ethereum network.Experimental results demonstrate that the proposed system can fully support multistep accreditation and automatic adjustment for certificate credit.
基金supported by the National"973" Program of China (No. 2010CB328300)the National Natural Science Foundation of China (Nos.600837004 and 60777010)+3 种基金the National "863" Program of China (Nos. 2009AA01Z253 and 2009AA01A347)the Chinese Postdoctoral Science Foundation (No.20090460593)the Shanghai Postdoctoral Science Foundation (No. 10R21411600)the Open Fund of Beijing University of Posts and Telecommunications, and the Shuguang Fund
文摘A novel scheme to generate, transmit, and receive an optical orthogonal frequency division multiplexing （OFDM） continuous phase modulation （CPM） signal, which is combining minimum shift keying （MSK） coding with OFDM optical modulation, for downlink application in a 4×2.5-Gb/s wavelength division multiplexing （WDM） passive optical access network, is proposed and experimentally validated. We also realize wavelength remodulation for carrying upstream on-off keying （OOK） data to reduce the cost budget at the optical network unit. The experimental results show that the power penalties for the downlink and the uplink data after transmission over 25-km SMF-28 fiber are 0.1 dB and smaller than 0.4 dB, respectively.
基金supported by the National"973" Program of China (No. 2010CB328300)the National Natural Science Foundation of China (Nos.600837004 and 60777010)+3 种基金the National "863" Program of China (Nos. 2009AA01Z253, 2009AA01A347, and2007AA01Z260)the Chinese Postdoctoral Science Foundation (No. 20090460593)Shanghai Postdoctoral Sci-ence Foundation (No. 10R21411600)the Open Fundof Beijing University of Posts and Telecommunications,and the Shuguang Fund
文摘A novel 40-Gb/s constant envelope optical frequency shift keying （FSK） transmitter and the transmission characteristics are investigated both by simulation and experiment. Meanwhile, to increase the spectrum efficiency of FSK, we propose a novel optical minimum-shift keying （MSK） scheme and analyze its per-formance compared with other MSK schemes and other traditional modulation formats. Simulation and experimental results show that the novel FSK scheme could be a potential candidate for the future high speed transmission and label switching systems. And the novel MSK scheme deserves future deep research for its potential excellent performance.
文摘A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.
基金supported by the National "973" Program of China(No.2010CB328300)the National Natural Science Foundation of China(Nos.61107064,61177071,and 600837004)+1 种基金the Doctoral Fund of Ministry of Education,the Open Fund of State Key Lab of ASIC&System(No.11MS009)the Open Fund of State Key Lab of Information Photonics and Optical Communications
文摘We experimentally demonstrate a 4-Gb/s radio-over-fiber （RoF） system with 40-kin fiber and 2-m wireless distance downstream at 100-GHz carrier. To the best of our knowledge, this is for the first time in China to realize optical wireless link at 100 GHz. In this letter, simple intensity modulator with direct detector （IM-DD） modulation is employed and optical power penalty afZer 40-kin single mode fiber （SMF）-28 and 2-m air link is 3.2 dB with bit-error-rate （BER） at 1 × 10- 9.
基金supported by the National Science Foundation of China(No.61571133)Key Project of Guangdong Province of China(No.2015B010113001)
文摘With the rapid development of the light-emitting diode （LED） industry, interest in visible light communication （VLC） is growing. The limited bandwidth of commercial LEDs is one of the main challenges to achieve high- speed VLC. In this Letter, a kind of bandwidth-efficient VLC system based on carrierless amplitude and phase （CAP） modulation is proposed, where a simple differential faster-than-Nyquist （FTN） pre-coding scheme is em- ployed to compress the spectrum and further improve the overall system baud rate. The system is experimentally demonstrated with a data rate of 1.47-Cb/s over 1.5 m free space transmission. The results indicate that an improvement of 80 Mbaud is achieved by FTN-CAP4 at 20% subband overlap and 40 Mbaud rate improvement by FTN-CAP16 at 7.5% subband overlap. Compared with traditional CAP, the FTN pre-coded CAP shows a better performance in spectral efficiency （SE） and intercarrier interference resistance. To the best of our knowl- edge, it is the first time to employ FTN pre-coded CAP in indoor high-data-rate VLC systems.
文摘In this Letter, we propose a novel constellation-shaping carrier-less amplitude and phase （CAP） modulation scheme to alleviate the systematic nonlinearity in visible light communication （VLC） systems. A simple geo- metric transformation shaping method is employed to convert the normal square lattice constellation into multi- ple circular constellations. The feasibility and performance are investigated and experimentally demonstrated by a 1.25 Gb/s CAP-modulated VLC system. The results indicate that the circular constellation has better resis- tance to systematic nonlinearity compared with a rectangular constellation. The dynamic range of input signal peak-to-peak values promotes 20% at a low bias voltage nonlinear area and 50% at a high bias voltage nonlinear area. To the best of our knowledge, this is the first time constellation-shaping CAP has ever been reported in indoor high data rate VLC systems.
基金supported by the National Program "973" of China (Nos. 2010CB328300)the National Natural Science Foundation of China (Nos . 600837004and 60777010)+2 种基金the National "863" Program of China(Nos. 2009AA01Z253 and 2009AA01A347)the Chinese Postdoctoral Science Foundation (No. 20090460593)the Shanghai Postdoctoral Science Foundation (No.10R21411600), and the Shuguang Fund
文摘We propose a novel advanced orthogonal modulation format dark return-to-zero frequency shift keying/differential phase shift keying （DRZ-FSK/DPSK） and its realization scheme. The DRZ-FSK/DPSK is generated by the combination of a 40-Gb/s return-to-zero （RZ） signal and a DRZ signal which is converted from the RZ using a semiconductor optical amplifier （SOA） based on nonlinear cross polarization rotation （XPR） and then re-modulated by high-bit-rate DPSK at 40 Gb/s. The feasibility of the scheme is exper-imentally demonstrated. Bit error rate （BER） results of the total 80-Gb/s DRZ-FSK/DPSK orthogonal modulation signal with a subsequent 100-km single-mode fiber （SMF） transmission link show its potential for future high-speed long-haul optical communication.
基金Project supported by the National Natural Science Foundation of China （No. 61404175）
文摘We propose a reeonfigurable control-bit generation algorithm for rotation and sub-word rotation operations. The algorithm uses a self-routing characteristic to configure an inverse butterfly network. In addition to being highly parallelized and inexpensive, the algorithm integrates the rotation-shift, bi-directional rotation-shift, and sub-word rotation-shift operations. To our best knowledge, this is the first scheme to accommodate a variety of rotation operations into the same architecture. We have developed the highly efficient reconfigurable rotation unit （HERRU） and synthesized it into the Semiconductor Manufacturing International Corporation （SMIC）＇s 65-nm process. The results show that the overall efficiency （relative areaxrelative latency） of our HERRU is higher by at least 23% than that of other designs with similar functions. When executing the bi-directional rotation operations alone, HERRU occupies a significantly smaller area with a lower latency than previously proposed designs.
文摘RSA and ellipse curve cryptography(ECC)algorithms are widely used in authentication,data security,and access control.In this paper,we analyze the basic operation of the ECC and RSA algorithms and optimize their modular multiplication and modular inversion algorithms.We then propose a reconfigurable modular operation architecture,with a mix-memory unit and double multiply-accumulate structures,to realize our unified,asymmetric cryptosystem structure in an operational unit.Synthesized with 55-nm CMOS process,our design runs at 588 MHz and requires only 437801µm2 of hardware resources.Our proposed design takes 21.92 and 23.36 mW for 2048-bit RSA modular multiplication and modular inversion respectively,as well as 16.16 and 15.88 mW to complete 512-bit ECC dual-field modular multiplication and modular inversion respectively.It is more energy-efficient and flexible than existing single algorithm units.Compared with existing multiple algorithm units,our proposed method shows better performance.The operation unit is embedded in a 64-bit RISC-V processor,realizing key generation,encryption and decryption,and digital signature functions of both RSA and ECC.Our proposed design takes 0.224 and 0.153 ms for 256-bit ECC point multiplication in G(p)and G(2^(m))respectively,as well as 0.96 ms to complete 1024-bit RSA exponentiation,meeting the demand for high energy efficiency.
