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Multiple-State Storage Capability of Stacked Chalcogenide Films (Si16Sb33Te51/Si4Sb45Te51/Si11Sb39Te50) for Phase Change Memory 被引量:1
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作者 赖云锋 冯洁 +6 位作者 乔保卫 黄晓刚 蔡燕飞 林殷茵 汤庭鳌 蔡炳初 陈邦明 《Chinese Physics Letters》 SCIE CAS CSCD 2006年第9期2516-2518,共3页
The multiple-state storage capability of phase change memory (PCM) is confirmed by using stacked chalcogenide films as the storage medium. The current-voltage characteristics and the resistance-current characteristi... The multiple-state storage capability of phase change memory (PCM) is confirmed by using stacked chalcogenide films as the storage medium. The current-voltage characteristics and the resistance-current characteristics of the PCM clearly indicate that four states can be stored in this stacked film structure. Qualitative analysis indicates that the multiple-state storage capability of this stacked film structure is due to successive crystallizations in different Si-Sb-Te layers triggered by different amplitude currents. 展开更多
关键词 RANDOM-ACCESS MEMORY DOPED GE2SB2TE5 FILMS OPTICAL DISK CRYSTALLIZATION
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Nitrogen and Silicon Co-Doping of Ge2Sb2Te5 Thin Films for Improving Phase Change Memory Performance
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作者 蔡燕飞 周鹏 +8 位作者 林殷茵 汤庭鳌 陈良尧 李晶 乔保卫 赖云峰 冯洁 蔡炳初 陈邦民 《Chinese Physics Letters》 SCIE CAS CSCD 2007年第3期781-783,共3页
Electrical properties and phase structures of (Si+N)-codoped Oe2Sb2Te5 (GST) for phase change memory are investigated to improve the memory performance. Compared to the films with N or Si dopants only in previous... Electrical properties and phase structures of (Si+N)-codoped Oe2Sb2Te5 (GST) for phase change memory are investigated to improve the memory performance. Compared to the films with N or Si dopants only in previous reports, the (Si+N)-doped GST has a remarkable improvement of crystalline resistivity of about 104mΩcm. The Fourier-transform infrared spectroscopy spectrum reveals the Si-N bonds formation in the film. X-ray diffraction patterns show that the grain size is reduced due to the crystallization inhibition of the amorphous GST by SiNx, which results in higher crystalline resistivity. This is very useful to reduce writing current for phase change memory applications. 展开更多
关键词 RANDOM-ACCESS MEMORY ELECTRICAL-PROPERTIES CRYSTALLIZATION IMPROVEMENT MODEL
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Ge1Sb2Te4 Based Chalcogenide Random Access Memory Array Fabricated by 0.18-μm CMOS Technology
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作者 张挺 宋志棠 +4 位作者 冯高明 刘波 吴良才 封松林 陈邦明 《Chinese Physics Letters》 SCIE CAS CSCD 2007年第3期790-792,共3页
Ge1Sb2Te4-based chalcogenide random access memory array, with a tungsten heating electrode of 260hm in diameter, is fabricated by 0.18-μm CMOS technology. Electrical performance of the device, as web as physical and ... Ge1Sb2Te4-based chalcogenide random access memory array, with a tungsten heating electrode of 260hm in diameter, is fabricated by 0.18-μm CMOS technology. Electrical performance of the device, as web as physical and electrical properties of GelSb2 Te4 thin film, is characterized. SET and RESET programming currents are 1.6 and 4.1 mA, respectively, when pulse width is 100 ns. Both the values are larger than those of the Ge2Sb2 Tesbased ones with the same structure and contact size. Endurance up to 106 cycles with a resistance ratio of about 100 has been achieved. 展开更多
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硅离子注入对Ge2Sb2Te5结构和电阻的影响 被引量:3
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作者 刘波 宋志棠 +2 位作者 封松林 Chen Bomy 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第z1期158-160,共3页
采用磁控射频溅射法制备了Ge2Sb2Te5薄膜,利用离子注入法研究了硅掺杂对薄膜结构和电阻性能的影响.研究发现,由于硅的掺杂,Ge2Sb2Te5薄膜的结构不仅保留了原有的面心立方低温晶相和六方高温晶相,而且出现了菱形六面体的Sb2Te3晶相;掺杂... 采用磁控射频溅射法制备了Ge2Sb2Te5薄膜,利用离子注入法研究了硅掺杂对薄膜结构和电阻性能的影响.研究发现,由于硅的掺杂,Ge2Sb2Te5薄膜的结构不仅保留了原有的面心立方低温晶相和六方高温晶相,而且出现了菱形六面体的Sb2Te3晶相;掺杂硅后,Ge2Sb2Te5薄膜的电阻有较大变化,晶态电阻的提高有利于降低非晶化相变过程的操作电流,薄膜电阻-温度稳定性的改善可保证有较宽的操作电流波动范围. 展开更多
关键词 Ge2Sb2Te5 硅离子注入掺杂 方块电阻
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Characteristics of Sn-Doped Ge2Sb2Te5 Films Used for Phase-Change Memory 被引量:3
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作者 徐成 刘波 +2 位作者 宋志棠 封松林 陈邦明 《Chinese Physics Letters》 SCIE CAS CSCD 2005年第11期2929-2932,共4页
Sn-doped Ge2Sb2Te5 thin films deposited on Si(100)/SiO2 substrates by rf magnetron sputtering are investigated by a differential scanning calorimeter, x-ray diffraction and sheet resistance measurement. The crystall... Sn-doped Ge2Sb2Te5 thin films deposited on Si(100)/SiO2 substrates by rf magnetron sputtering are investigated by a differential scanning calorimeter, x-ray diffraction and sheet resistance measurement. The crystallization temperatures of the 3.58 at.%, 6.92 at.% and 10.04 at.% Sn-doped Ge2Sb2Te5 thin films have decreases of 5.3, 6.1 and 0.9℃, respectively, which is beneficial to reduce the switching current for the amorphous-to-crystalline phase transition. Due to Sn-doping, the sheet resistance of crystalline Ge2Sb2Te5 thin films increases about 2-10 times, which may be useful to reduce the switching current for the amorphous-to-crystalline phase change. In addition, an obvious decreasing dispersibility for the sheet resistance of Sn-doped Ge2Sb2Te5 thin films in the crystalline state has been observed, which can play an important role in minimizing resistance difference for the phase-change memory cell element arrays. 展开更多
关键词 RANDOM-ACCESS MEMORY ION-BEAM METHOD ELECTRICAL-PROPERTIES OPTICAL-PROPERTIES CELL-ELEMENT RESISTANCE IMPLANTATION TRANSITION ALLOYS MEDIA
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Improvement of Electrical Properties of the Ge2Sb2Te5 Film by Doping Si for Phase-Change Random Access Memory 被引量:2
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作者 乔保卫 冯洁 +5 位作者 赖云锋 凌云 林殷茵 汤庭鳌 蔡炳初 陈邦明 《Chinese Physics Letters》 SCIE CAS CSCD 2006年第1期172-174,共3页
Si-doped Ge2Sb2Te5 films have been prepared by dc magnetron co-sputtering with Ge2Sb2Te5 and Si targets. The addition of Si in the Ge2Sb2Te5 film results in the increase of both crystallization temperature and phasetr... Si-doped Ge2Sb2Te5 films have been prepared by dc magnetron co-sputtering with Ge2Sb2Te5 and Si targets. The addition of Si in the Ge2Sb2Te5 film results in the increase of both crystallization temperature and phasetransition temperature from face-centred-cubic (fcc) phase to hexagonal (hex) phase. The resistivity of the Ge2Sb2Te5 film shows a significant increase with the Si doping. When doping 11.8 at.% of Si in the film, the resistivity after 460℃ annealing increases from 1 to 11 mΩ.cm and dynamic resistance increase from 64 to 99Ω compared to the undoped Ge2Sb2Te5 film. This is very helpful to writing current reduction of phase-change random access memory. 展开更多
关键词 NONVOLATILE MEMORY THIN-FILMS RESISTANCE ALLOYS
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Total Dose Radiation Tolerance of Phase Change Memory Cell with GeSbTe Alloy 被引量:1
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作者 吴良才 刘波 +3 位作者 宋志棠 冯高明 封松林 陈宝明 《Chinese Physics Letters》 SCIE CAS CSCD 2006年第9期2557-2559,共3页
Phase change memory (PCM) cell array is fabricated by a standard complementary metal-oxide-semiconductor process and the subsequent special fabrication technique. A chalcogenide Ge2Sb2Te5 film in thickness 50hm depo... Phase change memory (PCM) cell array is fabricated by a standard complementary metal-oxide-semiconductor process and the subsequent special fabrication technique. A chalcogenide Ge2Sb2Te5 film in thickness 50hm deposited by rf magnetron sputtering is used as storage medium for the PCM cell. Large snap-back effect is observed in current-voltage characteristics, indicating the phase transition from an amorphous state (higher resistance state) to the crystalline state (lower resistance state). The resistance of amorphous state is two orders of magnitude larger than that of the crystalline state from the resistance measurement, and the threshold current needed for phase transition of our fabricated PCM cell array is very low (only several μA). An x-ray total dose radiation test is carried out on the PCM cell array and the results show that this kind of PCM cell has excellent total dose radiation tolerance with total dose up to 2 ×10^6 rad(Si), which makes it attractive for space-based applications. 展开更多
关键词 AMORPHOUS THIN-FILMS RANDOM-ACCESS MEMORY GE2SB2TE5 FILMS ELECTRICAL-PROPERTIES NONVOLATILE GE20TE80-XBIX IMPLANTATION TEMPERATURE TRANSITION
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Study on the delamination of tungsten thin films on Sb2Te3 被引量:1
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作者 徐嘉庆 刘波 +2 位作者 宋志棠 封松林 Chen Bomyb 《Chinese Physics B》 SCIE EI CAS CSCD 2006年第8期1849-1854,共6页
To investigate the reliability of electrode materials for chalcogenide random access memory (C-RAM) applications, the geometry and time evolution of the worm-like delamination patterns on a tungsten/Sb2Te3 bilayer s... To investigate the reliability of electrode materials for chalcogenide random access memory (C-RAM) applications, the geometry and time evolution of the worm-like delamination patterns on a tungsten/Sb2Te3 bilayer system surface are observed by field emission scanning electronic microscope (FESEM) and optical microscopy. The tungsten film stress and interface toughness are estimated using a straight-side model. After confirming the instability of this system being due to large compressive stress stored in the tungsten film and relative poor interface adhesion, a preliminary solution as the inset of a TiN adhesion layer is presented to improve the system performances. 展开更多
关键词 C-RAM DELAMINATION ADHESION
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Si1Sb2Te3 phase change material for chalcogenide random access memory 被引量:1
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作者 张挺 宋志棠 +3 位作者 刘波 刘卫丽 封松林 陈邦明 《Chinese Physics B》 SCIE EI CAS CSCD 2007年第8期2475-2478,共4页
This paper investigated phase change Si1Sb2Te3 material for application of chalcogenide random access memory. Current-voltage performance was conducted to determine threshold current of phase change from amorphous pha... This paper investigated phase change Si1Sb2Te3 material for application of chalcogenide random access memory. Current-voltage performance was conducted to determine threshold current of phase change from amorphous phase to polycrystalline phase. The film holds a threshold current about 0.155 mA, which is smaller than the value 0.31 mA of Ge2Sb2Te5 film. Amorphous Si1Sb2Te3 changes to face-centred-cubic structure at ~ 180℃ and changes to hexagonal structure at ~ 270℃. Annealing temperature dependent electric resistivity of Si1Sb2Te3 film was studied by four-point probe method. Data retention of the films was characterized as well. 展开更多
关键词 phase change chalcogenide random access memory Si-Sb-Te
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Damascene Array Structure of Phase Change Memory Fabricated with Chemical Mechanical Polishing Method 被引量:1
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作者 刘奇斌 宋志棠 +3 位作者 张楷亮 王良咏 封松林 CHEN Bomy 《Chinese Physics Letters》 SCIE CAS CSCD 2006年第8期2296-2298,共3页
A damascene structure of phase change memory (PCM) is fabricated successfully with the chemical mechanical polishing (CMP) method, and the CMP of Ge2Sb2Te5 (GST) and Ti films is investigated. The polished surfac... A damascene structure of phase change memory (PCM) is fabricated successfully with the chemical mechanical polishing (CMP) method, and the CMP of Ge2Sb2Te5 (GST) and Ti films is investigated. The polished surface of wafer is analysed by scanning electron microscopy (SEM) and an energy dispersive spectrometer (EDS). The measurements show that the damascene device structure of phase change memory is achieved by the CMP process. After the top electrode is deposited, dc sweeping test on PCM reveals that the phase change can be observed. The threshold current of array cells varies between 0.90mA and 1.15mA. 展开更多
关键词 ION-BEAM METHOD CELL-ELEMENT
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Chalcogenide Random Access Memory Cell with Structure of W Sub-Microtube Heater Electrode 被引量:3
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作者 刘波 冯高明 +4 位作者 吴良才 宋志棠 刘奇斌 封松林 CHEN Bomy 《Chinese Physics Letters》 SCIE CAS CSCD 2007年第1期262-264,共3页
In order to reduce the reset current of cllalcogenide random access memory; a W sub-microtube heater electrode with outer/inner diameter of 260/100nm, which was fabricated with standard 0.184-μm technology, is propos... In order to reduce the reset current of cllalcogenide random access memory; a W sub-microtube heater electrode with outer/inner diameter of 260/100nm, which was fabricated with standard 0.184-μm technology, is proposed for the first time to achieve a reset current of about 0.5 mA. The reasons may be that sub-microtube increases the number of electrode edge and thermal efficiency is improved greatly because the thermal density on the edge of sub-microtube electrode is generally the highest. 展开更多
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Reactive Ion Etching as Cleaning Method Post Chemical Mechanical Polishing for Phase Change Memory Device
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作者 钟旻 宋志棠 +2 位作者 刘波 封松林 陈宝林 《Chinese Physics Letters》 SCIE CAS CSCD 2008年第2期762-764,共3页
In order to improve nano-scale phase change memory performance, a super-clean interface should be obtained after chemical mechanical polishing (CMP) of Ge2Sb2Te5 phase change films. We use reactive ion etching (RIE... In order to improve nano-scale phase change memory performance, a super-clean interface should be obtained after chemical mechanical polishing (CMP) of Ge2Sb2Te5 phase change films. We use reactive ion etching (RIE) as the cleaning method. The cleaning effect is analysed by scanning electron microscopy and an energy dispersive spectrometer. The results show that particle residue on the surface has been removed. Meanwhile, Ge2Sb2Te5 material stoichiometric content ratios are unchanged. After the top electrode is deposited, currentvoltage characteristics test demonstrates that the set threshold voltage is reduced from 13 V to 2.7V and the threshold current from 0.1 mA to 0.025 mA. Furthermore, we analyse the RIE cleaning principle and compare it with the ultrasonic method. 展开更多
关键词 CELL-ELEMENT BEAM METHOD
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用分离栅极闪存单元实现可编程逻辑阵列
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作者 Henry Om’mani Mandana Tadayoni +2 位作者 Nitya Thota Ian Yue Nhan Do 《中国集成电路》 2014年第12期50-53,共4页
我们开发了一种新型可配置逻辑阵列测试结构,它采用高度可伸缩且兼具功耗低和配置时间短两大优势的第3代分离栅极闪存单元。此分离栅极Super Flash配置元件(SCE)已通过90nm嵌入式闪存技术进行了演示。得到的SCE消除了对深奥的制造工... 我们开发了一种新型可配置逻辑阵列测试结构,它采用高度可伸缩且兼具功耗低和配置时间短两大优势的第3代分离栅极闪存单元。此分离栅极Super Flash配置元件(SCE)已通过90nm嵌入式闪存技术进行了演示。得到的SCE消除了对深奥的制造工艺、检测和SRAM电路的需求,并缩短了可编程阵列(PA)(例如,FPGA和CPLD)的配置时间。此外,SCE本身还具有SST分离栅极闪存技术的优点,包括紧凑的区域、低电压读操作、低功耗多晶硅间(pol y-t o-pol y)擦除、源极侧通道热电子(SSCHE)注入编程机制以及超高的可靠性。 展开更多
关键词 CPLD FPGA 可编程逻辑阵列 分离栅极闪存
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Si3.5Sb2Te3 Phase Change Material for Low-Power Phase Change Memory Application
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作者 任堃 饶峰 +8 位作者 宋志棠 吴良才 周夕淋 夏梦娇 刘波 封松林 席韡 姚栋宁 陈邦明 《Chinese Physics Letters》 SCIE CAS CSCD 2010年第10期206-209,共4页
Novel Si3.5Sb2Te3 phase change material for phase change memory is prepared by sputtering of Si and Sb2Te3 alloy targets. Crystalline Si3.5Sb2Te3 is a stable composite material consisting of amorphous Si and crystalli... Novel Si3.5Sb2Te3 phase change material for phase change memory is prepared by sputtering of Si and Sb2Te3 alloy targets. Crystalline Si3.5Sb2Te3 is a stable composite material consisting of amorphous Si and crystalline Sb2Te3, without separated Te phase. The thermally stable Si3.5Sb2Te3 material has data retention ability (10 years at 412K) better than that of the Ge2Sb2Te5 material (10 years at 383 K). Phase change memory device based on Si3.5Sb2Te3 is successfully fabricated, showing low power consumption. Up to 2.2 × 107 cycles of endurance have been achieved with a resistance ratio lager than 300. 展开更多
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氮掺杂Ge_2Sb_2Te_5相变存储器的多态存储功能 被引量:5
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作者 赖云锋 冯洁 +5 位作者 乔保卫 凌云 林殷茵 汤庭鳌 蔡炳初 陈邦明 《物理学报》 SCIE EI CAS CSCD 北大核心 2006年第8期4347-4352,共6页
通过反应溅射的方法,制备了N掺杂的Ge2Sb2Te5(NGST)薄膜,用作相变存储器的存储介质.研究表明,掺杂的N以GeN的形式存在,不仅束缚了Ge2Sb2Te5(GST)晶粒的长大也提高了GST的晶化温度和相变温度.利用NGST薄膜的非晶态、晶态面心立方相和晶... 通过反应溅射的方法,制备了N掺杂的Ge2Sb2Te5(NGST)薄膜,用作相变存储器的存储介质.研究表明,掺杂的N以GeN的形式存在,不仅束缚了Ge2Sb2Te5(GST)晶粒的长大也提高了GST的晶化温度和相变温度.利用NGST薄膜的非晶态、晶态面心立方相和晶态六方相的电阻率差异,能够在同一存储单元中存储三个状态,实现相变存储器的多态存储功能. 展开更多
关键词 相变存储器 多态存储 N掺杂 Ge2Sb2Te5
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相变存储器的高可靠性多值存储设计
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作者 洪洋 林殷茵 +1 位作者 汤庭鳌 Bomy Chen 《复旦学报(自然科学版)》 CAS CSCD 北大核心 2006年第1期49-53,72,共6页
基于相变存储器(PCM)已有的2T2R结构,提出一种以比值为导向的状态定义方法,以实现2T2R结构下PCM的多值存储.它在相变电阻具有4态可编写的能力下,可以实现单元内8态存储,同时对小尺寸验证,而对PCM存储电路的优化将使得PCM更具竞争力.同... 基于相变存储器(PCM)已有的2T2R结构,提出一种以比值为导向的状态定义方法,以实现2T2R结构下PCM的多值存储.它在相变电阻具有4态可编写的能力下,可以实现单元内8态存储,同时对小尺寸验证,而对PCM存储电路的优化将使得PCM更具竞争力.同样基于这种以比值为导向的状态定义,一种软硬件相结合的新型纠错码方法使得对全部数据位的错误监测成为可能. 展开更多
关键词 相变存储器 2T2R 多值存储 一维比值空间 校验纠错码
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相变存储器多态存储方法 被引量:4
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作者 刘欣 周鹏 +6 位作者 林殷茵 汤庭鳌 赖云峰 乔保卫 冯洁 蔡炳初 BOMY CHEN 《复旦学报(自然科学版)》 CAS CSCD 北大核心 2008年第1期95-100,共6页
提出两种实现相变存储器多值存储的方法.这两种方法基于新的机理,即通过存储单元结构或相变材料的改进来得到在传统"高阻态"和"低阻态"两态之间稳定的中间电阻状态.与传统实现相变多态存储的方法相比,利用这两种方... 提出两种实现相变存储器多值存储的方法.这两种方法基于新的机理,即通过存储单元结构或相变材料的改进来得到在传统"高阻态"和"低阻态"两态之间稳定的中间电阻状态.与传统实现相变多态存储的方法相比,利用这两种方法实现的多值相变存储,可以有效地提高多态存储的可靠性和抗噪声性能,有利于在提高存储密度的同时简化外围电路的设计,在实际应用中有良好的前景. 展开更多
关键词 微电子技术 相变存储器 多值存储 多值存储单元
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基于Si掺杂Sb2Te3薄膜的相变存储器研究 被引量:1
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作者 张祖发 张胤 +5 位作者 冯洁 蔡燕飞 林殷茵 蔡炳初 汤庭鳌 Bomy Chen 《物理学报》 SCIE EI CAS CSCD 北大核心 2007年第7期4224-4228,共5页
采用磁控三靶(Si,Sb及Te)共溅射法制备了Si掺杂Sb2Te3薄膜,作为对比,制备了Ge2Sb2Te5和Sb2Te3薄膜,并且采用微加工工艺制备了单元尺寸为10μm×10μm的存储器件原型来研究器件性能.研究表明,Si掺杂提高了Sb2Te3薄膜的晶化温度以及... 采用磁控三靶(Si,Sb及Te)共溅射法制备了Si掺杂Sb2Te3薄膜,作为对比,制备了Ge2Sb2Te5和Sb2Te3薄膜,并且采用微加工工艺制备了单元尺寸为10μm×10μm的存储器件原型来研究器件性能.研究表明,Si掺杂提高了Sb2Te3薄膜的晶化温度以及薄膜的晶态和非晶态电阻率,使得其非晶态与晶态电阻率之比达到106,提高了器件的电阻开/关比;同Ge2Sb2Te5薄膜相比,16at%Si掺杂Sb2Te3薄膜具有较低的熔点和更高的晶态电阻率,这有利于降低器件的RESET电流.研究还表明,采用16at%Si掺杂Sb2Te3薄膜作为存储介质的存储器器件原型具有记忆开关特性,可以在脉高3V、脉宽500ns的电脉冲下实现SET操作,在脉高4V、脉宽20ns的电脉冲下实现RESET操作,并能实现反复写/擦,而采用Ge2Sb2Te5薄膜的相同结构的器件不能实现RESET操作. 展开更多
关键词 相变存储器 硫系化合物 Si掺杂Sb2Te3 薄膜 SET/RESET转变
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Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance
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作者 董耀旗 孔蔚然 +2 位作者 Nhan Do 王序伦 李荣林 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第6期74-77,共4页
The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cel... The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance. 展开更多
关键词 split-gate flash ENDURANCE erase voltage
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