This paper presents another necessary condition about the optimum parti-tion on a finite set of samples. From this condition, a corresponding generalized sequential hao f k-means (GSHKM) clustering algorithm is built ...This paper presents another necessary condition about the optimum parti-tion on a finite set of samples. From this condition, a corresponding generalized sequential hao f k-means (GSHKM) clustering algorithm is built and many well-known clustering algorithms are found to be included in it. Under some assumptions the well-known MacQueen's SHKM (Sequential Hard K-Means)algorithm, FSCL (Frequency Sensitive Competitive Learning) algorithm and RPCL (Rival Penalized Competitive Learning) algorithm are derived. It is shown that FSCL in fact still belongs to the kind of GSHKM clustering algth rithm and is more suitable for producing means of K-partition of sample data,which is illustrated by numerical experiment. Meanwhile, some improvements on these algorithms are also given.展开更多
This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5 μm CMOS gate array The chipcan operate at 60MHz, and consumes less than 0.5Wat. The results are al...This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5 μm CMOS gate array The chipcan operate at 60MHz, and consumes less than 0.5Wat. The results are alsostudied, and a more precise model of delay time dmerence is proposed.展开更多
Because of high development costs of IC (Integrated Circuit) test programs,recycling ekisting test programs from one kind of ATE (Automatic Test Equip-ment) to another or generating directly from CAD simulation module...Because of high development costs of IC (Integrated Circuit) test programs,recycling ekisting test programs from one kind of ATE (Automatic Test Equip-ment) to another or generating directly from CAD simulation modules to ATEis more and more vauable. In this papert a new approach to migrating test pro-grams is presented. A virtual ATE model based on object-oriellted paradigm isdeveloped; it runs Test C++ (an intermediate test control language) programsand TeIF (Test Intermediate Format - an intermediate pattern), migrates testprograms among three kinds of ATE (Ando DIC8032, Schlumberger S15 andGenRad 1732) and gellerates test patterns from two kinds of CAD (Daisy andPanda) automatically.展开更多
Sorted constraint representation is a very useful representation in AI which combines class hierarchies and constraint networks. For such sorted constraint representation, a problem is how to generalize the idea of de...Sorted constraint representation is a very useful representation in AI which combines class hierarchies and constraint networks. For such sorted constraint representation, a problem is how to generalize the idea of default inheritance to constraint network, where the attributes in a class or between different classes interact with each other via the network. To give a formal account for the defeasible reasoning in such representation, a general sorted constraint logic is proposed, and a minimal-model semantics for the logic is presented.展开更多
文摘This paper presents another necessary condition about the optimum parti-tion on a finite set of samples. From this condition, a corresponding generalized sequential hao f k-means (GSHKM) clustering algorithm is built and many well-known clustering algorithms are found to be included in it. Under some assumptions the well-known MacQueen's SHKM (Sequential Hard K-Means)algorithm, FSCL (Frequency Sensitive Competitive Learning) algorithm and RPCL (Rival Penalized Competitive Learning) algorithm are derived. It is shown that FSCL in fact still belongs to the kind of GSHKM clustering algth rithm and is more suitable for producing means of K-partition of sample data,which is illustrated by numerical experiment. Meanwhile, some improvements on these algorithms are also given.
文摘This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5 μm CMOS gate array The chipcan operate at 60MHz, and consumes less than 0.5Wat. The results are alsostudied, and a more precise model of delay time dmerence is proposed.
文摘Because of high development costs of IC (Integrated Circuit) test programs,recycling ekisting test programs from one kind of ATE (Automatic Test Equip-ment) to another or generating directly from CAD simulation modules to ATEis more and more vauable. In this papert a new approach to migrating test pro-grams is presented. A virtual ATE model based on object-oriellted paradigm isdeveloped; it runs Test C++ (an intermediate test control language) programsand TeIF (Test Intermediate Format - an intermediate pattern), migrates testprograms among three kinds of ATE (Ando DIC8032, Schlumberger S15 andGenRad 1732) and gellerates test patterns from two kinds of CAD (Daisy andPanda) automatically.
文摘Sorted constraint representation is a very useful representation in AI which combines class hierarchies and constraint networks. For such sorted constraint representation, a problem is how to generalize the idea of default inheritance to constraint network, where the attributes in a class or between different classes interact with each other via the network. To give a formal account for the defeasible reasoning in such representation, a general sorted constraint logic is proposed, and a minimal-model semantics for the logic is presented.
