期刊文献+
共找到4篇文章
< 1 >
每页显示 20 50 100
Drop failure modes of Sn-3.0Ag-0.5Cu solder joints in wafer level chip scale package 被引量:7
1
作者 黄明亮 赵宁 +1 位作者 刘爽 何宜谦 《Transactions of Nonferrous Metals Society of China》 SCIE EI CAS CSCD 2016年第6期1663-1669,共7页
To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden... To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board (PCB) side, split between redistribution layer (RDL) and Cu under bump metallization (UBM), RDL fracture, bulk cracks and partial bulk and intermetallic compound (IMC) cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side. 展开更多
关键词 Sn-3.0Ag-0.5Cu wafer level chip scale package solder joint drop failure mode
在线阅读 下载PDF
A high-efficiency transformer-in-package isolated DC-DC converter using glass-based fan-out wafer-level packaging 被引量:3
2
作者 Lin Cheng Zuohuan Chen +1 位作者 Daquan Yu Dongfang Pan 《Fundamental Research》 CSCD 2024年第6期1407-1414,共8页
A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer a... A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2. 展开更多
关键词 Isolated DC-DC converter Transmitter(TX) Receiver(RX) TRANSFORMER Fan-out wafer level packaging(FOWLP) Power density Efficiency
原文传递
Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology
3
作者 曹毓涵 罗乐 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第8期164-168,共5页
A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding param... A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E. 展开更多
关键词 wafer level package Cu-Sn isothermal solidification technology hermeticity
原文传递
Synthesis and properties of a novel perfluorinated polyimide with high toughness,low dielectric constant and low dissipation factor
4
作者 Hangqian Wang Yao Zhang +4 位作者 Xialei Lv Jinhui Li Kuangyu Wang Guoping Zhang Rong Sun 《Industrial Chemistry & Materials》 2025年第5期587-595,共9页
With the development of high-frequency communication technologies,polyimide(PI)materials with a low dielectric constant(Dk)and low dissipation factor(Df)are urgently needed to reduce signal crosstalk and other transmi... With the development of high-frequency communication technologies,polyimide(PI)materials with a low dielectric constant(Dk)and low dissipation factor(Df)are urgently needed to reduce signal crosstalk and other transmission problems.The introduction of a trifluoromethyl group is a common strategy to reduce Dk and Df,but the bulky trifluoromethyl group would diminish stacking density and consequently lead to inferior mechanical properties.Herein,a novel diamine monomer,2,3,4,5,6-pentafluororo-3,5-bis(4-aminophenoxy)-1,1-biphenyl(5FBODA),was designed and synthesized using simple reactions.Subsequently,fluorinated diamine and dianhydride were copolymerized with 5FBODA to obtain a series of fluorinated polyimide(FPI)with excellent dielectric properties and good mechanical performances,particularly high elongation at break.The pentafluorophenyl side group showed an obvious electronwithdrawing effect and made the charge of the structure more balanced,which reduced the molecular polarization rate and charge concentration to some extent,significantly helping in reducing Dk at high frequency.As the 5FBODA content increased,the large lateral group restricted the movement of the main chain,constrained the dipole polarization,thereby effectively diminishing their Df.Moreover,when 20-30%5FBODA was added,the pentafluorophenyl side group increased the intermolecular forces,thereby enhancing the elongation at break while maintaining good thermal properties.These FPIs exhibited remarkable advantages for advanced microelectronic packaging applications,providing an innovative solution for the development of next-generation high-performance electronic materials. 展开更多
关键词 wafer level packaging Fluorinated polyimide Low dielectric High toughness
在线阅读 下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部