SAR ADC(Successive Approximation Register Analog Digital Converter)是一种低功耗、结构简单、性能可靠的ADC,其精度和采样速率的可选范围较大,因此被广泛应用于各种集成电路中。传统SAR ADC采用电容阵列提供模拟参考电压,但电容阵...SAR ADC(Successive Approximation Register Analog Digital Converter)是一种低功耗、结构简单、性能可靠的ADC,其精度和采样速率的可选范围较大,因此被广泛应用于各种集成电路中。传统SAR ADC采用电容阵列提供模拟参考电压,但电容阵列需要较大面积,因此降低了单位晶圆的产出率,增加了成本。文中采用一种已有R2R DAC(Digital Analog Converter)结构代替电容阵列提供模拟参考电压以减小电路面积。相比传统电阻DAC结构,R2R DAC结构功耗更小。在电路设计中增加翻转电路消除共模噪声,在版图绘制时加入保护环和赝管来确保匹配度与可靠性。在精度相同的情况下,SAR ADC电路有效面积减小了约35%。抽取寄生参数后仿真所得ADC的ENOB(Effective Number of Bits)为9.93 bit,SNDR(Signal-to-Noise-and-Distortion Ratio)为61.51 dB,且在不同PVT(Process Voltage Temperature)情况下仿真的误差均小于1 LSB(Least Significant Number)。展开更多
This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture...This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection.The calibration method is simple in structure and fast in convergence.The correction of errors in each bit is independent of those in the previous bit.A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC.An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead.The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration.With calibration,the INL and DNL are-0.813/0.938 and-0.625/0.688,respectively.展开更多
针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control l...This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.展开更多
针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier...针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。展开更多
文摘SAR ADC(Successive Approximation Register Analog Digital Converter)是一种低功耗、结构简单、性能可靠的ADC,其精度和采样速率的可选范围较大,因此被广泛应用于各种集成电路中。传统SAR ADC采用电容阵列提供模拟参考电压,但电容阵列需要较大面积,因此降低了单位晶圆的产出率,增加了成本。文中采用一种已有R2R DAC(Digital Analog Converter)结构代替电容阵列提供模拟参考电压以减小电路面积。相比传统电阻DAC结构,R2R DAC结构功耗更小。在电路设计中增加翻转电路消除共模噪声,在版图绘制时加入保护环和赝管来确保匹配度与可靠性。在精度相同的情况下,SAR ADC电路有效面积减小了约35%。抽取寄生参数后仿真所得ADC的ENOB(Effective Number of Bits)为9.93 bit,SNDR(Signal-to-Noise-and-Distortion Ratio)为61.51 dB,且在不同PVT(Process Voltage Temperature)情况下仿真的误差均小于1 LSB(Least Significant Number)。
文摘This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection.The calibration method is simple in structure and fast in convergence.The correction of errors in each bit is independent of those in the previous bit.A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC.An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead.The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration.With calibration,the INL and DNL are-0.813/0.938 and-0.625/0.688,respectively.
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
基金supported by Qingdao Hi-image Technologies Co., Ltdin part by the NSFC of China under Grant 62174149, 61974118, 62004156the National Key R&D Program of China under Grant 2022YFC2404902
文摘This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.
文摘针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。
