A two stage scan architecture is proposed to do low power and low test application cost scan testing. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-f...A two stage scan architecture is proposed to do low power and low test application cost scan testing. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops. The scan flip-flop in the multiple scan chain and the scan flip-flop driven by it are assigned the same values for all test vectors. Scan flip-flops in the multiple scan chains and those in the second stage use separate clock signals, but the design for testability technqiue needs only one clock. The proposed scan architecture localizes test power consumption to the multiple scan chains during test application. Test signals assigned to scan flip-fiops in the multiple scan chains are applied to the scan flip-flops in the second stage after the test vector has been applied to the multiple scan chains. This technique can make test power consumption very small.展开更多
Side channel attack may result in user key leakage as scan test techniques are applied for crypto-graphic chips. Many secure scan designs have been proposed to protect the user key. This paper meticulously selects thr...Side channel attack may result in user key leakage as scan test techniques are applied for crypto-graphic chips. Many secure scan designs have been proposed to protect the user key. This paper meticulously selects three current scan test techniques, analyses their advantages and disadvantages and also compares them in security and area overhead. Users can choose one of them according to the requirements and further combination can be implemented to achieve better performance.展开更多
In this paper, ultrasonic C-scan test of spot welds for stainless steel has been studied. It is concluded that large scanning step length contributes to high testing efficiency, however, the low-resolution C-scan imag...In this paper, ultrasonic C-scan test of spot welds for stainless steel has been studied. It is concluded that large scanning step length contributes to high testing efficiency, however, the low-resolution C-scan image generated cannot be used to assess spot welding quality reliably. Based on bicubic image interpolation, the C-scan image in low resolution with the large step length 1 000 ~xm is subdivided and reconstructed. By this means, the C-scan image resolution is greatly enhanced and testing results obtained are satisfactory, realizing rapid assessment of spot welds. The results of rapid ultrasonic C-scan test fit the actual metallographic measured value well. Mean value of normal distribution of error statistics is O. 006 67, and the standard deviation is O. 087 11. Rapid ultrasonic C-scan test based on image interpolation is of high accuracy and excellent stability.展开更多
To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Glo...To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.展开更多
A new nondestructive test method-Impact Echo Scanning was introduced. Application of this method on pavement structure test was discussed. A method to increase the measurement accuracy of the test on multi-layers was ...A new nondestructive test method-Impact Echo Scanning was introduced. Application of this method on pavement structure test was discussed. A method to increase the measurement accuracy of the test on multi-layers was proposed, and was verified by field test. The test results show that the basic structural information can obtained rapidly and accurately by 3-D scanning of the impact echo system.展开更多
The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next t...The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.展开更多
An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generatio...An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.展开更多
Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test da...Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.展开更多
Background: Detection of malignant liver mass is very important for the treatment modalities. Objective: The purpose of the present study was to establish the usefulness of CT scan in the diagnosis of malignant hepati...Background: Detection of malignant liver mass is very important for the treatment modalities. Objective: The purpose of the present study was to establish the usefulness of CT scan in the diagnosis of malignant hepatic mass. Methodology: This cross sectional study was carried out in the Department of Radiology and Imaging at Mymensingh Medical College Hospital (MMCH), Mymensingh, Banghabandhu Sheikh Mujib Medical University (B中央人民政府), Dhaka and Dhaka Medical College Hospital (DMCH), Dhaka during the period of 1st January 2006 to 31st December 2007. Patients admitted in the Department of Medicine and Department of Hepatobiliary of MMCH, B中央人民政府, and DMCH with the clinical diagnosis of fever, abdominal pain, anorexia, nausea/vomiting, loss of appetite, jaundice, weight loss and ascites were selected as study population. CT scan and histopathology were performed to all the patients. Result: A total number of 50 patients were recruited for this study. Mean age of all patients was 51.28 ± 14 years with a range of 17 year to 78 years. Among all patients 28 had multiple lesion, of them 71.4% was malignant and 28.6% was benign. On the other side 22 patients had solitary lesion, of them 36.4% was malignant and 63.6% was benign展开更多
The advanced integrated circuits have been widely used in various situations including the Internet of Things,wireless communication,etc.But its manufacturing process exists unreliability,so cryptographic chips must b...The advanced integrated circuits have been widely used in various situations including the Internet of Things,wireless communication,etc.But its manufacturing process exists unreliability,so cryptographic chips must be rigorously tested.Due to scan testing provides high test coverage,it is applied to the testing of cryptographic integrated circuits.However,while providing good controllability and observability,it also provides attackers with a backdoor to steal keys.In the text,a novel protection scheme is put forward to resist scan-based attacks,in which we first use the responses generated by a strong physical unclonable function circuit to solidify fuseantifuse structures in a non-linear shift register(NLSR),then determine the scan input code according to the configuration of the fuse-antifuse structures and the styles of connection between the NLSR cells and the scan cells.If the key is right,the chip can be tested normally;otherwise,the data in the scan chain cannot be propagated normally,it is also impossible for illegal users to derive the desired scan data.The proposed technique not only enhances the security of cryptographic chips,but also incurs acceptable overhead.展开更多
基金This workis supported in part by JSPS under grant L03540and the National Science Foundation of China under grant60373009
文摘A two stage scan architecture is proposed to do low power and low test application cost scan testing. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops. The scan flip-flop in the multiple scan chain and the scan flip-flop driven by it are assigned the same values for all test vectors. Scan flip-flops in the multiple scan chains and those in the second stage use separate clock signals, but the design for testability technqiue needs only one clock. The proposed scan architecture localizes test power consumption to the multiple scan chains during test application. Test signals assigned to scan flip-fiops in the multiple scan chains are applied to the scan flip-flops in the second stage after the test vector has been applied to the multiple scan chains. This technique can make test power consumption very small.
文摘Side channel attack may result in user key leakage as scan test techniques are applied for crypto-graphic chips. Many secure scan designs have been proposed to protect the user key. This paper meticulously selects three current scan test techniques, analyses their advantages and disadvantages and also compares them in security and area overhead. Users can choose one of them according to the requirements and further combination can be implemented to achieve better performance.
文摘In this paper, ultrasonic C-scan test of spot welds for stainless steel has been studied. It is concluded that large scanning step length contributes to high testing efficiency, however, the low-resolution C-scan image generated cannot be used to assess spot welding quality reliably. Based on bicubic image interpolation, the C-scan image in low resolution with the large step length 1 000 ~xm is subdivided and reconstructed. By this means, the C-scan image resolution is greatly enhanced and testing results obtained are satisfactory, realizing rapid assessment of spot welds. The results of rapid ultrasonic C-scan test fit the actual metallographic measured value well. Mean value of normal distribution of error statistics is O. 006 67, and the standard deviation is O. 087 11. Rapid ultrasonic C-scan test based on image interpolation is of high accuracy and excellent stability.
文摘To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.
基金Funded by the National Natural Science Foundation of China(No.50472042) Doctoral Base Fund of Ministry of Education of China(No.20050497010)
文摘A new nondestructive test method-Impact Echo Scanning was introduced. Application of this method on pavement structure test was discussed. A method to increase the measurement accuracy of the test on multi-layers was proposed, and was verified by field test. The test results show that the basic structural information can obtained rapidly and accurately by 3-D scanning of the impact echo system.
基金the National Natural Science Foundation of China (Grant Nos.60373009 and 60425203)
文摘The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.
基金This project was supported by the National Natural Science Foundation of China (90407007).
文摘An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.
文摘Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.
文摘Background: Detection of malignant liver mass is very important for the treatment modalities. Objective: The purpose of the present study was to establish the usefulness of CT scan in the diagnosis of malignant hepatic mass. Methodology: This cross sectional study was carried out in the Department of Radiology and Imaging at Mymensingh Medical College Hospital (MMCH), Mymensingh, Banghabandhu Sheikh Mujib Medical University (B中央人民政府), Dhaka and Dhaka Medical College Hospital (DMCH), Dhaka during the period of 1st January 2006 to 31st December 2007. Patients admitted in the Department of Medicine and Department of Hepatobiliary of MMCH, B中央人民政府, and DMCH with the clinical diagnosis of fever, abdominal pain, anorexia, nausea/vomiting, loss of appetite, jaundice, weight loss and ascites were selected as study population. CT scan and histopathology were performed to all the patients. Result: A total number of 50 patients were recruited for this study. Mean age of all patients was 51.28 ± 14 years with a range of 17 year to 78 years. Among all patients 28 had multiple lesion, of them 71.4% was malignant and 28.6% was benign. On the other side 22 patients had solitary lesion, of them 36.4% was malignant and 63.6% was benign
基金This work was funded by the Researchers Supporting Project No.(RSP2022R509)King Saud University,Riyadh,Saudi Arabia.In additionthe Natural Science Foundation of Hunan Province under Grant no.2020JJ5604,2022JJ2029 and 2020JJ4622the National Natural Science Foundation of China under Grant no.62172058.
文摘The advanced integrated circuits have been widely used in various situations including the Internet of Things,wireless communication,etc.But its manufacturing process exists unreliability,so cryptographic chips must be rigorously tested.Due to scan testing provides high test coverage,it is applied to the testing of cryptographic integrated circuits.However,while providing good controllability and observability,it also provides attackers with a backdoor to steal keys.In the text,a novel protection scheme is put forward to resist scan-based attacks,in which we first use the responses generated by a strong physical unclonable function circuit to solidify fuseantifuse structures in a non-linear shift register(NLSR),then determine the scan input code according to the configuration of the fuse-antifuse structures and the styles of connection between the NLSR cells and the scan cells.If the key is right,the chip can be tested normally;otherwise,the data in the scan chain cannot be propagated normally,it is also impossible for illegal users to derive the desired scan data.The proposed technique not only enhances the security of cryptographic chips,but also incurs acceptable overhead.
