Bernoulli’s law is applied to the closed streamlines of a smoke ring, and the centrifugal force of the curved flow is balanced by a pressure gradient. Two equations in two unknowns, pressure and velocity, are combine...Bernoulli’s law is applied to the closed streamlines of a smoke ring, and the centrifugal force of the curved flow is balanced by a pressure gradient. Two equations in two unknowns, pressure and velocity, are combined into one equation in one unknown, velocity. Solving the governing equation algebraically produces a radial shear in the velocity such that the speed decreases outward inversely as the radius increases, which is the main result. Measurements are needed to verify the predicted structure of the velocity field.展开更多
Starting from well established results in pure mathematics, mainly transfinite set theory, E-infinity algebra over operads, fuzzy manifolds and fuzzy Lie symmetry groups, we construct an exact Weyl scaling for the hig...Starting from well established results in pure mathematics, mainly transfinite set theory, E-infinity algebra over operads, fuzzy manifolds and fuzzy Lie symmetry groups, we construct an exact Weyl scaling for the highly structured E-infinity rings corresponding to E-infinity theory of high energy physics. The final result is an exact expression for the energy density of the cosmos which agrees with previous analysis as well as accurate cosmological measurements and observations, such as COBE, WMAP and Planck. The paper is partially intended as a vivid demonstration of the power of pure mathematics in physics and cosmology.展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
文摘Bernoulli’s law is applied to the closed streamlines of a smoke ring, and the centrifugal force of the curved flow is balanced by a pressure gradient. Two equations in two unknowns, pressure and velocity, are combined into one equation in one unknown, velocity. Solving the governing equation algebraically produces a radial shear in the velocity such that the speed decreases outward inversely as the radius increases, which is the main result. Measurements are needed to verify the predicted structure of the velocity field.
文摘Starting from well established results in pure mathematics, mainly transfinite set theory, E-infinity algebra over operads, fuzzy manifolds and fuzzy Lie symmetry groups, we construct an exact Weyl scaling for the highly structured E-infinity rings corresponding to E-infinity theory of high energy physics. The final result is an exact expression for the energy density of the cosmos which agrees with previous analysis as well as accurate cosmological measurements and observations, such as COBE, WMAP and Planck. The paper is partially intended as a vivid demonstration of the power of pure mathematics in physics and cosmology.
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
