Cybertwin-enabled 6th Generation(6G)network is envisioned to support artificial intelligence-native management to meet changing demands of 6G applications.Multi-Agent Deep Reinforcement Learning(MADRL)technologies dri...Cybertwin-enabled 6th Generation(6G)network is envisioned to support artificial intelligence-native management to meet changing demands of 6G applications.Multi-Agent Deep Reinforcement Learning(MADRL)technologies driven by Cybertwins have been proposed for adaptive task offloading strategies.However,the existence of random transmission delay between Cybertwin-driven agents and underlying networks is not considered in related works,which destroys the standard Markov property and increases the decision reaction time to reduce the task offloading strategy performance.In order to address this problem,we propose a pipelining task offloading method to lower the decision reaction time and model it as a delay-aware Markov Decision Process(MDP).Then,we design a delay-aware MADRL algorithm to minimize the weighted sum of task execution latency and energy consumption.Firstly,the state space is augmented using the lastly-received state and historical actions to rebuild the Markov property.Secondly,Gate Transformer-XL is introduced to capture historical actions'importance and maintain the consistent input dimension dynamically changed due to random transmission delays.Thirdly,a sampling method and a new loss function with the difference between the current and target state value and the difference between real state-action value and augmented state-action value are designed to obtain state transition trajectories close to the real ones.Numerical results demonstrate that the proposed methods are effective in reducing reaction time and improving the task offloading performance in the random-delay Cybertwin-enabled 6G networks.展开更多
The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass ...The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.展开更多
The yield stress of waxy crude oil is a fundamental parameter in the calculation of pipelining technique and analysis of flow safety for the heated oil transported through pipeline.Daqing crude oil was studied and the...The yield stress of waxy crude oil is a fundamental parameter in the calculation of pipelining technique and analysis of flow safety for the heated oil transported through pipeline.Daqing crude oil was studied and the variation of yield stress with shear history was explored through simulation experiment of pipelining.It is found that the effect of throughput variation or shear rate on yield stress is not obvious.With the decrease of final dynamic cooling temperature,the yield stress of waxy crude oil decreases,but there exists a little increase at the beginning.The prediction model of yield stress for waxy crude oil under the condition of shutdown is developed and it can be used to predict the yield stress of Daqing crude oil at certain heating temperature,final dynamic cooling temperature and measurement temperature.For the 139 groups of yield stress data of Daqing crude oil from the simulation experiment of pipelining,the result of prediction with this model shows that the average relative deviation between the yield stress measured and predicted is 30.27%,and the coefficient of correlation is 0.962 3.展开更多
Communication optimization is very important for imporoving performance of parallel programs A communication optimization method called HVMP(Half Vector Message Ripelining) is presented. In comparison with the widelyu...Communication optimization is very important for imporoving performance of parallel programs A communication optimization method called HVMP(Half Vector Message Ripelining) is presented. In comparison with the widelyused vector message pipelining, HVMP can get better tradeoff between reducing and hiding communication overhead,and eliminate the communication barrier of barrier synchronization problems[1]. For parallel Systems with low bandwidth such as cluster of workstations and barrier synchronization problems with large amount of communication, HVMPmethod can get good performance.展开更多
Software process is a framework for effective and timely delivery of software system. The framework plays a crucial role for software success. However, the development of large-scale software still faces the crisis of...Software process is a framework for effective and timely delivery of software system. The framework plays a crucial role for software success. However, the development of large-scale software still faces the crisis of high risks, low quality, high costs and long cycle time. This paper proposed a three-phase parallel-pipelining software process model for improving speed and productivity, and reducing software costs and risks without sacrificing software quality. In this model, two strategies were presented. One strategy, based on subsystem-cost priority, was used to prevent software development cost wasting and to reduce software complexity as well; the other strategy, used for balancing subsystem complexity, was designed to reduce the software complexity in the later development stages. Moreover, the proposed function-detailed and workload-simplified subsystem pipelining software process model presents much higher parallelity than the concurrent incremental model. Finally, the component-based product line technology not only ensures software quality and further reduces cycle time, software costs, and software risks but also sufficiently and rationally utilizes previous software product resources and enhances the competition ability of software development organizations.展开更多
On the basis of Floyd algorithm with the extended path matrix, a parallel algorithm which resolves all-pair shortest path （APSP） problem on cluster environment is analyzed and designed. Meanwhile, the parallel APSP ...On the basis of Floyd algorithm with the extended path matrix, a parallel algorithm which resolves all-pair shortest path （APSP） problem on cluster environment is analyzed and designed. Meanwhile, the parallel APSP pipelining algorithm makes full use of overlapping technique between computation and communication. Compared with broadcast operation, the parallel algorithm reduces communication cost. This algorithm has been implemented on MPI on PC-cluster. The theoretical analysis and experimental results show that the parallel algorithm is an efficient and scalable algorithm.展开更多
An adaptive pipelining scheme for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoder for high definition(HD) applications is proposed to solve data hazard problems coming from the data dependenci...An adaptive pipelining scheme for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoder for high definition(HD) applications is proposed to solve data hazard problems coming from the data dependencies in CABAC decoding process.An efficiency model of CABAC decoding pipeline is derived according to the analysis of a common pipeline.Based on that,several adaptive strategies are provided.The pipelining scheme with these strategies can be adaptive to different types of syntax elements(SEs) and the pipeline will not stall during decoding process when these strategies are adopted.In addition,the decoder proposed can fully support H.264/AVC high4:2:2 profile and the experimental results show that the efficiency of decoder is much higher than other architectures with one engine.Taking both performance and cost into consideration,our design makes a good tradeoff compared with other work and it is sufficient for HD real-time decoding.展开更多
Communication overhead is an important factor in massively parallel processing systems and it has a dramatic influence on the performance of systems. If it can be implemented as quickly as possible, then the performan...Communication overhead is an important factor in massively parallel processing systems and it has a dramatic influence on the performance of systems. If it can be implemented as quickly as possible, then the performance of systems can be greatly improved. Based on the TORUS interconnection network, this paper presents the pipelining broadcasting, which reduces the broadcasting delay and improve the performance of systems.展开更多
This paper offers a new method to solve the problem of software pipelininsr on nested loops. We first introduce our new software pipelininog method. Ruminate Method, which can optimize program with nested loops. We al...This paper offers a new method to solve the problem of software pipelininsr on nested loops. We first introduce our new software pipelininog method. Ruminate Method, which can optimize program with nested loops. We also outline an algorithm to realize it and introduce the hardware support we designed. The performance of Ruminate Method is analyzed at the end of this paper with the aid of our preliminary experimental result.展开更多
This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline ...This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.展开更多
Underwater pipeline inspection plays a vital role in the proactive maintenance and management of critical marine infrastructure and subaquatic systems.However,the inspection of underwater pipelines presents a challeng...Underwater pipeline inspection plays a vital role in the proactive maintenance and management of critical marine infrastructure and subaquatic systems.However,the inspection of underwater pipelines presents a challenge due to factors such as light scattering,absorption,restricted visibility,and ambient noise.The advancement of deep learning has introduced powerful techniques for processing large amounts of unstructured and imperfect data collected from underwater environments.This study evaluated the efficacy of the You Only Look Once(YOLO)algorithm,a real-time object detection and localization model based on convolutional neural networks,in identifying and classifying various types of pipeline defects in underwater settings.YOLOv8,the latest evolution in the YOLO family,integrates advanced capabilities,such as anchor-free detection,a cross-stage partial network backbone for efficient feature extraction,and a feature pyramid network+path aggregation network neck for robust multi-scale object detection,which make it particularly well-suited for complex underwater environments.Due to the lack of suitable open-access datasets for underwater pipeline defects,a custom dataset was captured using a remotely operated vehicle in a controlled environment.This application has the following assets available for use.Extensive experimentation demonstrated that YOLOv8 X-Large consistently outperformed other models in terms of pipe defect detection and classification and achieved a strong balance between precision and recall in identifying pipeline cracks,rust,corners,defective welds,flanges,tapes,and holes.This research establishes the baseline performance of YOLOv8 for underwater defect detection and showcases its potential to enhance the reliability and efficiency of pipeline inspection tasks in challenging underwater environments.展开更多
With its growth in spacecraft control applications,the microcontroller(MCU)becomes increasingly sensitive to radiation and the risks of system failure.In a radiation environment,the MCU is vulnerable to impacts from h...With its growth in spacecraft control applications,the microcontroller(MCU)becomes increasingly sensitive to radiation and the risks of system failure.In a radiation environment,the MCU is vulnerable to impacts from high-energy particles,which can lead to single-event effect(SEE)that disrupt normal system operations.The pipeline of MCU,being the core structure of the system,is particularly susceptible to single-event upset(SEU)and potentially causes execution failures.However,existing radiation-hardening techniques offer limited effectiveness for pipelines.To enhance SEU resistance,this study focused on a 32-bit MCU core with eight pipeline stages,proposing a pipeline hardening approach that utilizes lockstep technology to improve fault tolerance.Signals from two processors were compared including register write data,register contents and pre-fetched instructions.Any discrepancies triggered error flags to indicate faults.When an error flag was raised,recovery was initiated through an interrupt.The interrupt handler then retrieved state information from the advanced peripheral bus(APB)slave module to restore the CPU's operational state and resume execution.By combining hardware-based state preservation with software-driven error recovery,the proposed solution demonstrated significant improvements in fault tolerance rates and performance compared to traditional checkpoint-based techniques.After completing the pipeline hardening design,a fault injection platform was utilized in this paper to simulate real-world error conditions on internal processor modules.The platform was developed based on the circuit's register-transfer-level(RTL)design and statistical results.The fault injection platform was performed by automatically finding all registers within the target design.The register values were forced to upset at the tens of nanoseconds scale in the RTL description of the circuit's design.After running the circuit's functional simulation,the statistics of the faults in registers were displayed on the platform,which evaluated the influence of SEU.The vulnerability of SEU in the circuit could be observed from the results of the soft error statistics.The post-hardening soft error rates were then measured and compared to pre-hardening data,providing a quantitative evaluation of the improvements.Using this method,the soft error rates of the modules in the MCU core such as PFU,DPU,and Cache AXIM are 40.07%,26.36%,and 27.29%respectively before hardening.The soft error rates of modules mentioned above are reduced to 0%,0.69%,and 1.11%after hardening.The hardened and non-hardened designs of the entire core were implemented in FPGA.The total resource utilization of the triple mode redundancy(TMR)is 111984,as indicated by the number of look-up tables(LUTs)and registers consumed in the FPGA.The total resource utilization of this work is 78034,and the ratio of resource utilization between this work and TMR is approximately 69.68%.The error recovery time for the hardened MCU processor was analyzed using the completion cycles of a bubble sort algorithm as a benchmark.In this paper,the average recovery cycle using the software checkpoint roll-back method is 36479.06,and the average recovery cycle using this work is 26922.5.The ratio of recovery cycles between this work and checkpoint roll-back is about 73.8%.Assessments through random fault injection and FPGA implementation indicate that this approach effectively reduces processor faults caused by soft errors while optimizing resource utilization and efficiency over triplemodular redundancy.展开更多
This research conducts a comprehensive experimental study of the entire filling system process at the Weishan Lake Rare Earth Mine(WSLREM)in Shandong Province,encompassing tailings thickening,feeding,slurry preparatio...This research conducts a comprehensive experimental study of the entire filling system process at the Weishan Lake Rare Earth Mine(WSLREM)in Shandong Province,encompassing tailings thickening,feeding,slurry preparation,and pipeline transportation.It proposes a complete and efficient upgrade solution for an intelligent paste filling system.The results show that the F1 flocculant was selected to prepare a flocculant solution with a solution concentration of 0.1%.The unit consumption is set to 25 g·t^(-1),and the flocculation and sedimentation effects are optimal when the mass concentration is 15%,with an underflow concentration of 62%.The selection experiment of cementitious material shows that the effect of using new cementitious material is better than that of traditional 32.5R Portland cement.At the same time,rheological experiments on the filling slurry were carried out,and the filling transportation pressure was studied by combining theoretical calculations with numerical simulations.The research results have guiding significance for the debugging of filling pumps and the selection of a filling pipeline.After the application of industrial transformation,the underflow concentration of the sand silo was 64%–66%,the slurry concentration was 68%–72%,the addition range of the cementing material was 1∶16–1∶4,and the filling capacity was 40–60 m^(3)·h^(-1).The intelligent upgrade and transformation of the filling system have yielded remarkable results,providing significant reference value for the intelligent filling transformation of similar mines.展开更多
Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Th...Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Thace Software Pipelining,targeted to the instruction-level parallel processors such as Very Long Instruc-tion Word (VLIW) and superscalar machines. Thace software pipelining applies a global code scheduling technique to compact the original loop body. The re-sulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or call be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promis-ing in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.展开更多
Dynamic neural network(NN)techniques are increasingly important because they facilitate deep learning techniques with more complex network architectures.However,existing studies,which predominantly optimize the static...Dynamic neural network(NN)techniques are increasingly important because they facilitate deep learning techniques with more complex network architectures.However,existing studies,which predominantly optimize the static computational graphs by static scheduling methods,usually focus on optimizing static neural networks in deep neural network(DNN)accelerators.We analyze the execution process of dynamic neural networks and observe that dynamic features introduce challenges for efficient scheduling and pipelining in existing DNN accelerators.We propose DyPipe,a holistic approach to optimizing dynamic neural network inferences in enhanced DNN accelerators.DyPipe achieves significant performance improvements for dynamic neural networks while it introduces negligible overhead for static neural networks.Our evaluation demonstrates that DyPipe achieves 1.7x speedup on dynamic neural networks and maintains more than 96%performance for static neural networks.展开更多
Reconfigurable computing tries to achieve the balance between high efficiency of custom computing and flexibility of general-purpose computing. This paper presents the implementation techniques in LEAP, a coarse-grain...Reconfigurable computing tries to achieve the balance between high efficiency of custom computing and flexibility of general-purpose computing. This paper presents the implementation techniques in LEAP, a coarse-grained reconfigurable array, and proposes a speculative execution mechanism for dynamic loop scheduling with the goal of one iteration per cycle and implementation techniques to support decoupling synchronization between the token generator and the collector. This paper also in- troduces the techniques of exploiting both data dependences of intra- and inter-iteration, with the help of two instructions for special data reuses in the loop-carried dependences. The experimental results show that the number of memory accesses reaches on average 3% of an RISC processor simulator with no memory optimization. In a practical image matching application, LEAP architecture achieves about 34 times of speedup in execution cycles, compared with general-purpose processors.展开更多
The increasing occurrence of corrosion-related damage in steel pipelines has led to the growing use of composite-based repair techniques as an efficient alternative to traditional replacement methods.Computer modeling...The increasing occurrence of corrosion-related damage in steel pipelines has led to the growing use of composite-based repair techniques as an efficient alternative to traditional replacement methods.Computer modeling and structural analysis were performed for the repair reinforcement of a steel pipeline with a composite bandage.A preliminary analysis of possible contact interaction schemes was implemented based on the theory of cylindrical shells,taking into account transverse shear deformations.The finite element method was used for a detailed study of the stress state of the composite bandage and the reinforced section of the pipeline.The limit state of the reinforced section was assessed based on the von Mises criterion for steel and the Tsai-Wu criterion for composites.The effectiveness of the repair was demonstrated on a pipeline whose wall thickness had decreased by 20%as a result of corrosion damage.At a nominal pressure of P=6 MPa,the maximum normal stress in the weakened area reached 381 MPa.The installation of a composite bandage reduced this stress to 312 MPa,making the repaired section virtually as strong as the undamaged pipeline.Due to the linearity of the problem,the results obtained can be easily used to find critical internal pressure values.展开更多
Ice crystal icing is an important cause of accidents in aircraft engines.Ice formation in aircraft engines can cause internal blades to freeze,affecting the quality of the air flow field and blocking the flow path.On ...Ice crystal icing is an important cause of accidents in aircraft engines.Ice formation in aircraft engines can cause internal blades to freeze,affecting the quality of the air flow field and blocking the flow path.On the other hand,the entry of ice crystal particles into the combustion chamber can cause a decrease in temperature or even flameout,leading to engine surge or shutdown.Therefore,it is necessary to conduct multiphase flow tests on ice crystals for aircraft components such as aircraft engines.Conducting ice crystal multiphase flow tests on aircraft is an effective research method,but it requires the construction of an ice crystal multiphase flow test platform that meets relevant technical requirements.The paper focuses on the relevant experimental requirements and combines wind tunnel test structures to conduct multiphase flow numerical simulations on various forms of jet pipelines,obtaining particle motion distribution results.After comparison,the optimal form of jet structure is obtained,providing the best selection scheme for the design of relevant wind tunnel structures.展开更多
In ultraviolet cured-in-place-pipe(UV-CIPP)pipeline rehabilitation,resin performance critically determines repair effectiveness.Current UV-curable resins exhibit high volatile organic compound(VOC)emissions and inadeq...In ultraviolet cured-in-place-pipe(UV-CIPP)pipeline rehabilitation,resin performance critically determines repair effectiveness.Current UV-curable resins exhibit high volatile organic compound(VOC)emissions and inadequate post-cure toughness,which compromise fatigue resistance during service.To address these issues,we synthesized hydroxyl-terminated polyurethane acrylate prepolymers using diphenylmethane diisocyanate(MDI),polypropylene glycol(PPG),and hydroxyethyl methacrylate(HEMA).Fourier transform infrared spectroscopy(FTIR)confirmed successful prepolymer synthesis.We developed UV-curable resins by incorporating various crosslinking monomers and optimized the formulations through mechanical property analysis.Testing revealed that the polyurethane-acrylic UV-cured resin system combines polyurethane's mechanical excellence with acrylics'high UV-curing activity.The PPG200/MDI/HEMA formulation achieved superior performance,with a tensile strength of 55.31 MPa,an impact toughness of 22.7 kJ/m^(2),and a heat deflection temperature(HDT)of 132℃.The optimized system eliminates volatile components while maintaining high reactivity,addressing critical limitations in trenchless pipeline rehabilitation.The improved mechanical properties meet the operational demands of underground pipes,suggesting practical applicability in trenchless pipeline repair.展开更多
基金funded by the National Key Research and Development Program of China under Grant 2019YFB1803301Beijing Natural Science Foundation (L202002)。
文摘Cybertwin-enabled 6th Generation(6G)network is envisioned to support artificial intelligence-native management to meet changing demands of 6G applications.Multi-Agent Deep Reinforcement Learning(MADRL)technologies driven by Cybertwins have been proposed for adaptive task offloading strategies.However,the existence of random transmission delay between Cybertwin-driven agents and underlying networks is not considered in related works,which destroys the standard Markov property and increases the decision reaction time to reduce the task offloading strategy performance.In order to address this problem,we propose a pipelining task offloading method to lower the decision reaction time and model it as a delay-aware Markov Decision Process(MDP).Then,we design a delay-aware MADRL algorithm to minimize the weighted sum of task execution latency and energy consumption.Firstly,the state space is augmented using the lastly-received state and historical actions to rebuild the Markov property.Secondly,Gate Transformer-XL is introduced to capture historical actions'importance and maintain the consistent input dimension dynamically changed due to random transmission delays.Thirdly,a sampling method and a new loss function with the difference between the current and target state value and the difference between real state-action value and augmented state-action value are designed to obtain state transition trajectories close to the real ones.Numerical results demonstrate that the proposed methods are effective in reducing reaction time and improving the task offloading performance in the random-delay Cybertwin-enabled 6G networks.
文摘The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.
基金Project(07E1007) supported by the Youth Innovation Foundation for Petroleum Science and Technology of China National Petroleum CorportationProject(2006AA09Z357) supported by the National High Technology Research and Development of China
文摘The yield stress of waxy crude oil is a fundamental parameter in the calculation of pipelining technique and analysis of flow safety for the heated oil transported through pipeline.Daqing crude oil was studied and the variation of yield stress with shear history was explored through simulation experiment of pipelining.It is found that the effect of throughput variation or shear rate on yield stress is not obvious.With the decrease of final dynamic cooling temperature,the yield stress of waxy crude oil decreases,but there exists a little increase at the beginning.The prediction model of yield stress for waxy crude oil under the condition of shutdown is developed and it can be used to predict the yield stress of Daqing crude oil at certain heating temperature,final dynamic cooling temperature and measurement temperature.For the 139 groups of yield stress data of Daqing crude oil from the simulation experiment of pipelining,the result of prediction with this model shows that the average relative deviation between the yield stress measured and predicted is 30.27%,and the coefficient of correlation is 0.962 3.
文摘Communication optimization is very important for imporoving performance of parallel programs A communication optimization method called HVMP(Half Vector Message Ripelining) is presented. In comparison with the widelyused vector message pipelining, HVMP can get better tradeoff between reducing and hiding communication overhead,and eliminate the communication barrier of barrier synchronization problems[1]. For parallel Systems with low bandwidth such as cluster of workstations and barrier synchronization problems with large amount of communication, HVMPmethod can get good performance.
文摘Software process is a framework for effective and timely delivery of software system. The framework plays a crucial role for software success. However, the development of large-scale software still faces the crisis of high risks, low quality, high costs and long cycle time. This paper proposed a three-phase parallel-pipelining software process model for improving speed and productivity, and reducing software costs and risks without sacrificing software quality. In this model, two strategies were presented. One strategy, based on subsystem-cost priority, was used to prevent software development cost wasting and to reduce software complexity as well; the other strategy, used for balancing subsystem complexity, was designed to reduce the software complexity in the later development stages. Moreover, the proposed function-detailed and workload-simplified subsystem pipelining software process model presents much higher parallelity than the concurrent incremental model. Finally, the component-based product line technology not only ensures software quality and further reduces cycle time, software costs, and software risks but also sufficiently and rationally utilizes previous software product resources and enhances the competition ability of software development organizations.
基金the National Natural Science Foundation of China under Grant No. 60671033.
文摘On the basis of Floyd algorithm with the extended path matrix, a parallel algorithm which resolves all-pair shortest path （APSP） problem on cluster environment is analyzed and designed. Meanwhile, the parallel APSP pipelining algorithm makes full use of overlapping technique between computation and communication. Compared with broadcast operation, the parallel algorithm reduces communication cost. This algorithm has been implemented on MPI on PC-cluster. The theoretical analysis and experimental results show that the parallel algorithm is an efficient and scalable algorithm.
基金Supported by the National Natural Science Foundation of China(No.61076021)the National Basic Research Program of China(No.2009CB320903)China Postdoctoral Science Foundation(No.2012M511364)
文摘An adaptive pipelining scheme for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoder for high definition(HD) applications is proposed to solve data hazard problems coming from the data dependencies in CABAC decoding process.An efficiency model of CABAC decoding pipeline is derived according to the analysis of a common pipeline.Based on that,several adaptive strategies are provided.The pipelining scheme with these strategies can be adaptive to different types of syntax elements(SEs) and the pipeline will not stall during decoding process when these strategies are adopted.In addition,the decoder proposed can fully support H.264/AVC high4:2:2 profile and the experimental results show that the efficiency of decoder is much higher than other architectures with one engine.Taking both performance and cost into consideration,our design makes a good tradeoff compared with other work and it is sufficient for HD real-time decoding.
文摘Communication overhead is an important factor in massively parallel processing systems and it has a dramatic influence on the performance of systems. If it can be implemented as quickly as possible, then the performance of systems can be greatly improved. Based on the TORUS interconnection network, this paper presents the pipelining broadcasting, which reduces the broadcasting delay and improve the performance of systems.
文摘This paper offers a new method to solve the problem of software pipelininsr on nested loops. We first introduce our new software pipelininog method. Ruminate Method, which can optimize program with nested loops. We also outline an algorithm to realize it and introduce the hardware support we designed. The performance of Ruminate Method is analyzed at the end of this paper with the aid of our preliminary experimental result.
基金supported in part by the National R&D Program for Major Research Instruments of China(Grant No:62027814)the National Natural Science Foundation of China(Grant No:62104054)+2 种基金the Natural Science Foundation of Heilongjiang Province(Grant No:F2018010)the Postdoctoral Science Foundation of Heilongjiang Province,China(No:LBH-Z20133)the Fundamental Research Funds for The Central Universities,China(3072021CF0806)。
文摘This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.
文摘Underwater pipeline inspection plays a vital role in the proactive maintenance and management of critical marine infrastructure and subaquatic systems.However,the inspection of underwater pipelines presents a challenge due to factors such as light scattering,absorption,restricted visibility,and ambient noise.The advancement of deep learning has introduced powerful techniques for processing large amounts of unstructured and imperfect data collected from underwater environments.This study evaluated the efficacy of the You Only Look Once(YOLO)algorithm,a real-time object detection and localization model based on convolutional neural networks,in identifying and classifying various types of pipeline defects in underwater settings.YOLOv8,the latest evolution in the YOLO family,integrates advanced capabilities,such as anchor-free detection,a cross-stage partial network backbone for efficient feature extraction,and a feature pyramid network+path aggregation network neck for robust multi-scale object detection,which make it particularly well-suited for complex underwater environments.Due to the lack of suitable open-access datasets for underwater pipeline defects,a custom dataset was captured using a remotely operated vehicle in a controlled environment.This application has the following assets available for use.Extensive experimentation demonstrated that YOLOv8 X-Large consistently outperformed other models in terms of pipe defect detection and classification and achieved a strong balance between precision and recall in identifying pipeline cracks,rust,corners,defective welds,flanges,tapes,and holes.This research establishes the baseline performance of YOLOv8 for underwater defect detection and showcases its potential to enhance the reliability and efficiency of pipeline inspection tasks in challenging underwater environments.
文摘With its growth in spacecraft control applications,the microcontroller(MCU)becomes increasingly sensitive to radiation and the risks of system failure.In a radiation environment,the MCU is vulnerable to impacts from high-energy particles,which can lead to single-event effect(SEE)that disrupt normal system operations.The pipeline of MCU,being the core structure of the system,is particularly susceptible to single-event upset(SEU)and potentially causes execution failures.However,existing radiation-hardening techniques offer limited effectiveness for pipelines.To enhance SEU resistance,this study focused on a 32-bit MCU core with eight pipeline stages,proposing a pipeline hardening approach that utilizes lockstep technology to improve fault tolerance.Signals from two processors were compared including register write data,register contents and pre-fetched instructions.Any discrepancies triggered error flags to indicate faults.When an error flag was raised,recovery was initiated through an interrupt.The interrupt handler then retrieved state information from the advanced peripheral bus(APB)slave module to restore the CPU's operational state and resume execution.By combining hardware-based state preservation with software-driven error recovery,the proposed solution demonstrated significant improvements in fault tolerance rates and performance compared to traditional checkpoint-based techniques.After completing the pipeline hardening design,a fault injection platform was utilized in this paper to simulate real-world error conditions on internal processor modules.The platform was developed based on the circuit's register-transfer-level(RTL)design and statistical results.The fault injection platform was performed by automatically finding all registers within the target design.The register values were forced to upset at the tens of nanoseconds scale in the RTL description of the circuit's design.After running the circuit's functional simulation,the statistics of the faults in registers were displayed on the platform,which evaluated the influence of SEU.The vulnerability of SEU in the circuit could be observed from the results of the soft error statistics.The post-hardening soft error rates were then measured and compared to pre-hardening data,providing a quantitative evaluation of the improvements.Using this method,the soft error rates of the modules in the MCU core such as PFU,DPU,and Cache AXIM are 40.07%,26.36%,and 27.29%respectively before hardening.The soft error rates of modules mentioned above are reduced to 0%,0.69%,and 1.11%after hardening.The hardened and non-hardened designs of the entire core were implemented in FPGA.The total resource utilization of the triple mode redundancy(TMR)is 111984,as indicated by the number of look-up tables(LUTs)and registers consumed in the FPGA.The total resource utilization of this work is 78034,and the ratio of resource utilization between this work and TMR is approximately 69.68%.The error recovery time for the hardened MCU processor was analyzed using the completion cycles of a bubble sort algorithm as a benchmark.In this paper,the average recovery cycle using the software checkpoint roll-back method is 36479.06,and the average recovery cycle using this work is 26922.5.The ratio of recovery cycles between this work and checkpoint roll-back is about 73.8%.Assessments through random fault injection and FPGA implementation indicate that this approach effectively reduces processor faults caused by soft errors while optimizing resource utilization and efficiency over triplemodular redundancy.
基金Supported by the National Natural Science Foundation of China(52004152)Shandong Provincial Natural Science Foundation(ZR2024ME006,ZR2023QE133,ZR2020QE100)+2 种基金Small and Medium-sized Technology Enterprises in Shandong Province(2022TSGC2077)Shandong College Youth Science and Technology Support Program(2023KJ149)National Key Laboratory Open Project Open Fund(2023-JSKSSYS-06)。
文摘This research conducts a comprehensive experimental study of the entire filling system process at the Weishan Lake Rare Earth Mine(WSLREM)in Shandong Province,encompassing tailings thickening,feeding,slurry preparation,and pipeline transportation.It proposes a complete and efficient upgrade solution for an intelligent paste filling system.The results show that the F1 flocculant was selected to prepare a flocculant solution with a solution concentration of 0.1%.The unit consumption is set to 25 g·t^(-1),and the flocculation and sedimentation effects are optimal when the mass concentration is 15%,with an underflow concentration of 62%.The selection experiment of cementitious material shows that the effect of using new cementitious material is better than that of traditional 32.5R Portland cement.At the same time,rheological experiments on the filling slurry were carried out,and the filling transportation pressure was studied by combining theoretical calculations with numerical simulations.The research results have guiding significance for the debugging of filling pumps and the selection of a filling pipeline.After the application of industrial transformation,the underflow concentration of the sand silo was 64%–66%,the slurry concentration was 68%–72%,the addition range of the cementing material was 1∶16–1∶4,and the filling capacity was 40–60 m^(3)·h^(-1).The intelligent upgrade and transformation of the filling system have yielded remarkable results,providing significant reference value for the intelligent filling transformation of similar mines.
文摘Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Thace Software Pipelining,targeted to the instruction-level parallel processors such as Very Long Instruc-tion Word (VLIW) and superscalar machines. Thace software pipelining applies a global code scheduling technique to compact the original loop body. The re-sulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or call be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promis-ing in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.
基金supported by the Beijing Natural Science Foundation under Grant No.JQ18013the National Natural Science Foundation of China under Grant Nos.61925208,61732007,61732002 and 61906179+1 种基金the Strategic Priority Research Program of Chinese Academy of Sciences(CAS)under Grant No.XDB32050200the Youth Innovation Promotion Association CAS,Beijing Academy of Artificial Intelligence(BAAI)and Xplore Prize.
文摘Dynamic neural network(NN)techniques are increasingly important because they facilitate deep learning techniques with more complex network architectures.However,existing studies,which predominantly optimize the static computational graphs by static scheduling methods,usually focus on optimizing static neural networks in deep neural network(DNN)accelerators.We analyze the execution process of dynamic neural networks and observe that dynamic features introduce challenges for efficient scheduling and pipelining in existing DNN accelerators.We propose DyPipe,a holistic approach to optimizing dynamic neural network inferences in enhanced DNN accelerators.DyPipe achieves significant performance improvements for dynamic neural networks while it introduces negligible overhead for static neural networks.Our evaluation demonstrates that DyPipe achieves 1.7x speedup on dynamic neural networks and maintains more than 96%performance for static neural networks.
基金Supported by the National Natural Science Foundation of China (Grant No. 60633050, 60621003)the National High Technology Researchand Development Program of China (Grant No. 2007AA01Z06)
文摘Reconfigurable computing tries to achieve the balance between high efficiency of custom computing and flexibility of general-purpose computing. This paper presents the implementation techniques in LEAP, a coarse-grained reconfigurable array, and proposes a speculative execution mechanism for dynamic loop scheduling with the goal of one iteration per cycle and implementation techniques to support decoupling synchronization between the token generator and the collector. This paper also in- troduces the techniques of exploiting both data dependences of intra- and inter-iteration, with the help of two instructions for special data reuses in the loop-carried dependences. The experimental results show that the number of memory accesses reaches on average 3% of an RISC processor simulator with no memory optimization. In a practical image matching application, LEAP architecture achieves about 34 times of speedup in execution cycles, compared with general-purpose processors.
文摘The increasing occurrence of corrosion-related damage in steel pipelines has led to the growing use of composite-based repair techniques as an efficient alternative to traditional replacement methods.Computer modeling and structural analysis were performed for the repair reinforcement of a steel pipeline with a composite bandage.A preliminary analysis of possible contact interaction schemes was implemented based on the theory of cylindrical shells,taking into account transverse shear deformations.The finite element method was used for a detailed study of the stress state of the composite bandage and the reinforced section of the pipeline.The limit state of the reinforced section was assessed based on the von Mises criterion for steel and the Tsai-Wu criterion for composites.The effectiveness of the repair was demonstrated on a pipeline whose wall thickness had decreased by 20%as a result of corrosion damage.At a nominal pressure of P=6 MPa,the maximum normal stress in the weakened area reached 381 MPa.The installation of a composite bandage reduced this stress to 312 MPa,making the repaired section virtually as strong as the undamaged pipeline.Due to the linearity of the problem,the results obtained can be easily used to find critical internal pressure values.
文摘Ice crystal icing is an important cause of accidents in aircraft engines.Ice formation in aircraft engines can cause internal blades to freeze,affecting the quality of the air flow field and blocking the flow path.On the other hand,the entry of ice crystal particles into the combustion chamber can cause a decrease in temperature or even flameout,leading to engine surge or shutdown.Therefore,it is necessary to conduct multiphase flow tests on ice crystals for aircraft components such as aircraft engines.Conducting ice crystal multiphase flow tests on aircraft is an effective research method,but it requires the construction of an ice crystal multiphase flow test platform that meets relevant technical requirements.The paper focuses on the relevant experimental requirements and combines wind tunnel test structures to conduct multiphase flow numerical simulations on various forms of jet pipelines,obtaining particle motion distribution results.After comparison,the optimal form of jet structure is obtained,providing the best selection scheme for the design of relevant wind tunnel structures.
基金Funded by the National Natural Science Foundation of China(No.52473077)China Three Gorges Corporation(No.202403190)。
文摘In ultraviolet cured-in-place-pipe(UV-CIPP)pipeline rehabilitation,resin performance critically determines repair effectiveness.Current UV-curable resins exhibit high volatile organic compound(VOC)emissions and inadequate post-cure toughness,which compromise fatigue resistance during service.To address these issues,we synthesized hydroxyl-terminated polyurethane acrylate prepolymers using diphenylmethane diisocyanate(MDI),polypropylene glycol(PPG),and hydroxyethyl methacrylate(HEMA).Fourier transform infrared spectroscopy(FTIR)confirmed successful prepolymer synthesis.We developed UV-curable resins by incorporating various crosslinking monomers and optimized the formulations through mechanical property analysis.Testing revealed that the polyurethane-acrylic UV-cured resin system combines polyurethane's mechanical excellence with acrylics'high UV-curing activity.The PPG200/MDI/HEMA formulation achieved superior performance,with a tensile strength of 55.31 MPa,an impact toughness of 22.7 kJ/m^(2),and a heat deflection temperature(HDT)of 132℃.The optimized system eliminates volatile components while maintaining high reactivity,addressing critical limitations in trenchless pipeline rehabilitation.The improved mechanical properties meet the operational demands of underground pipes,suggesting practical applicability in trenchless pipeline repair.
