Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, the...Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.展开更多
针对微特电机驱动控制系统中,双有源桥(dual active bridge,DAB)变换器在高频调制过程中易产生较大电流应力,导致器件温升高、寿命衰减及负载扰动下系统稳定性下降等问题,本文提出一种改进型双移相优化调制策略。该方法基于双有源桥拓扑...针对微特电机驱动控制系统中,双有源桥(dual active bridge,DAB)变换器在高频调制过程中易产生较大电流应力,导致器件温升高、寿命衰减及负载扰动下系统稳定性下降等问题,本文提出一种改进型双移相优化调制策略。该方法基于双有源桥拓扑,建立双移相调制下的功率传输模型与电流应力数学模型,采用拉格朗日乘数法求解最优移相比组合,并进一步推导多功率场景下的电流应力解析表达式;在控制器设计方面,引入电感电流内环补偿机制,提高系统对电机驱动过程中负载变化的动态响应能力。MATLAB/Simulink仿真结果表明,该方法在典型微特电机负载工况下能有效降低变换器的电流应力,缩短暂态响应时间,并改善输出电压纹波,对提升微特电机控制系统的稳态与暂态性能具有良好效果,为高效能电机驱动供电模块的优化设计提供理论依据。展开更多
The low level radio frequency(LLRF) system for booster accelerator at Shanghai Synchrotron Radiation Facility(SSRF) was upgraded by a digital controller based on field programmable gate array(FPGA) technology.Paramete...The low level radio frequency(LLRF) system for booster accelerator at Shanghai Synchrotron Radiation Facility(SSRF) was upgraded by a digital controller based on field programmable gate array(FPGA) technology.Parameters of voltage, frequency and field flatness in the two 5-cell cavities are controlled to meet the requirements of booster. In this article, the ramping curve of cavity voltage, amplitude and phase control loop with vector sum of the two 5-cell cavities, tuning loop and field flatness loop are analyzed and discussed in detail.A different method in tuning loop is adopted due to the limitations of ADC channels. The function realizes energy ramping of electron beam from 150 Me V to 3.5 Ge V with a repetition rate of 2 Hz. With the new LLRF controller, the phase stability at ramping mode in 10 hours long operation is improved from ±1.5°(RMS) with open loop to ±0.15°(RMS) with close loop, while the detuning phase and field flatness are maintained to within ±2°and ±1%, respectively.展开更多
This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence ...This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.展开更多
The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sa...The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.展开更多
This paper presents a new inverter based on three-phase Boost/Buck-boost single-stage inverter. The basic configuration of the new topology and their fundamental principle are firstly introduced, the method of design ...This paper presents a new inverter based on three-phase Boost/Buck-boost single-stage inverter. The basic configuration of the new topology and their fundamental principle are firstly introduced, the method of design double-loop controller and sliding mode controller are clarified, analyzed and compared in the following. Finally the validity and feasibility of the new topology are tested by simulation. The results indicate that regulation of the voltage transfer ratio and output frequency can be realized optionally by the new converter, furthermore the harmonic distortion of waveform is low. So the inherent drawback of low voltage transfer ratio of traditional converter is effectively settled. This study may provide inspiration for further engineering application.展开更多
文摘Active power filter (APF) using novel virtual line-flux-linkage oriented control strategy can not only realizes no phase-locked-loop (PLL) control, but also achieves a good inhibitory effect to interfere. However, there are some problems in the conventional method, such as the error of amplitude, the shift of phase angle and the non-determinacy of initial oriented angle. In this paper, two one-order low-pass filters are adopted instead of the pure integrator in the virtual line-flux-linkage observer, which can steady the phase and amplitude. Furthermore, an original scheme of harmonics detection under the rotating coordinate is advanced based on the simplified space vector pulse width modulation (SVPWM) strategy. Meanwhile, by using the new SVPWM algorithm, the voltage space vector diagram of the three-level inverter can be simplified and applied into that of two-level inverter, and this makes the control for Neutral Point potential easier.
文摘针对微特电机驱动控制系统中,双有源桥(dual active bridge,DAB)变换器在高频调制过程中易产生较大电流应力,导致器件温升高、寿命衰减及负载扰动下系统稳定性下降等问题,本文提出一种改进型双移相优化调制策略。该方法基于双有源桥拓扑,建立双移相调制下的功率传输模型与电流应力数学模型,采用拉格朗日乘数法求解最优移相比组合,并进一步推导多功率场景下的电流应力解析表达式;在控制器设计方面,引入电感电流内环补偿机制,提高系统对电机驱动过程中负载变化的动态响应能力。MATLAB/Simulink仿真结果表明,该方法在典型微特电机负载工况下能有效降低变换器的电流应力,缩短暂态响应时间,并改善输出电压纹波,对提升微特电机控制系统的稳态与暂态性能具有良好效果,为高效能电机驱动供电模块的优化设计提供理论依据。
基金Supported by the National Natural Science Foundation of China(No.11335014)
文摘The low level radio frequency(LLRF) system for booster accelerator at Shanghai Synchrotron Radiation Facility(SSRF) was upgraded by a digital controller based on field programmable gate array(FPGA) technology.Parameters of voltage, frequency and field flatness in the two 5-cell cavities are controlled to meet the requirements of booster. In this article, the ramping curve of cavity voltage, amplitude and phase control loop with vector sum of the two 5-cell cavities, tuning loop and field flatness loop are analyzed and discussed in detail.A different method in tuning loop is adopted due to the limitations of ADC channels. The function realizes energy ramping of electron beam from 150 Me V to 3.5 Ge V with a repetition rate of 2 Hz. With the new LLRF controller, the phase stability at ramping mode in 10 hours long operation is improved from ±1.5°(RMS) with open loop to ±0.15°(RMS) with close loop, while the detuning phase and field flatness are maintained to within ±2°and ±1%, respectively.
文摘This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.
文摘The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.
文摘This paper presents a new inverter based on three-phase Boost/Buck-boost single-stage inverter. The basic configuration of the new topology and their fundamental principle are firstly introduced, the method of design double-loop controller and sliding mode controller are clarified, analyzed and compared in the following. Finally the validity and feasibility of the new topology are tested by simulation. The results indicate that regulation of the voltage transfer ratio and output frequency can be realized optionally by the new converter, furthermore the harmonic distortion of waveform is low. So the inherent drawback of low voltage transfer ratio of traditional converter is effectively settled. This study may provide inspiration for further engineering application.
