In this work,the GaN p-MISFET with LPCVD-SiN_(x) is studied as a gate dielectric to improve device performance.By changing the Si/N stoichiometry of SiN_(x),it is found that the channel hole mobility can be effectivel...In this work,the GaN p-MISFET with LPCVD-SiN_(x) is studied as a gate dielectric to improve device performance.By changing the Si/N stoichiometry of SiN_(x),it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN_(x) gate dielectric,which leads to a respectably improved drive current of GaN p-FET.The record high channel mobility of 19.4 cm2/(V∙s)was achieved in the device featuring an Enhancement-mode channel.Benefiting from the significantly improved channel mobility,the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm,while simultaneously featuring a negative threshold-voltage(VTH)of–2.3 V(defining at a stringent criteria of 10μA/mm).The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm.This suggests that a decent E-mode operation of the fabricated p-FET is obtained.In addition,the VTH shows excellent stability,while the threshold-voltage hysteresisΔVTH is as small as 0.1 V for a gate voltage swing up to–10 V,which is among the best results reported in the literature.The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN_(x) is a promising approach to improve the device performance of GaN p-MISFET.展开更多
In this letter,an enhancement-mode(E-mode)GaN p-channel field-effect transistor(p-FET)with a high current den-sity of−4.9 mA/mm based on a O_(3)-Al_(2)O_(3)/HfO_(2)(5/15 nm)stacked gate dielectric was demonstrated on ...In this letter,an enhancement-mode(E-mode)GaN p-channel field-effect transistor(p-FET)with a high current den-sity of−4.9 mA/mm based on a O_(3)-Al_(2)O_(3)/HfO_(2)(5/15 nm)stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure.Attributed to the p++-GaN capping layer,a good linear ohmic I−V characteristic fea-turing a low-contact resistivity(ρc)of 1.34×10^(−4)Ω·cm^(2) was obtained.High gate leakage associated with the HfO_(2)high-k gate dielectric was effectively blocked by the 5-nm O_(3)-Al_(2)O_(3)insertion layer grown by atomic layer deposition,contributing to a high ION/IOFF ratio of 6×10^(6)and a remarkably reduced subthreshold swing(SS)in the fabricated p-FETs.The proposed structure is compelling for energy-efficient GaN complementary logic(CL)circuits.展开更多
In this study,we present the development of self-aligned p-channel Ga N back gate injection transistors(SA-BGITs)that exhibit a high ON-state current.This achievement is primarily attributed to the conductivity modula...In this study,we present the development of self-aligned p-channel Ga N back gate injection transistors(SA-BGITs)that exhibit a high ON-state current.This achievement is primarily attributed to the conductivity modulation effect of the 2-D electron gas(2DEG,the back gate)beneath the 2-D hole gas(2DHG)channel.SA-BGITs with a gate length of 1μm have achieved an impressive peak drain current(I_(D,MAX))of 9.9 m A/mm.The fabricated SA-BGITs also possess a threshold voltage of 0.15 V,an exceptionally minimal threshold hysteresis of 0.2 V,a high switching ratio of 10~7,and a reduced ON-resistance(RON)of 548Ω·mm.Additionally,the SA-BGITs exhibit a steep sub-threshold swing(SS)of 173 mV/dec,further highlighting their suitability for integration into Ga N logic circuits.展开更多
Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are ...Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.展开更多
基金This work was supported in part by the Natural Science Foundation of China under Grant 62174019in part by the Guangdong Basic and Applied Basic Research Foundation China under Grant 2021B1515140039in part by the Zhuhai Industry-University Research Cooperation Project under Grant ZH22017001210041PWC.
文摘In this work,the GaN p-MISFET with LPCVD-SiN_(x) is studied as a gate dielectric to improve device performance.By changing the Si/N stoichiometry of SiN_(x),it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN_(x) gate dielectric,which leads to a respectably improved drive current of GaN p-FET.The record high channel mobility of 19.4 cm2/(V∙s)was achieved in the device featuring an Enhancement-mode channel.Benefiting from the significantly improved channel mobility,the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm,while simultaneously featuring a negative threshold-voltage(VTH)of–2.3 V(defining at a stringent criteria of 10μA/mm).The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm.This suggests that a decent E-mode operation of the fabricated p-FET is obtained.In addition,the VTH shows excellent stability,while the threshold-voltage hysteresisΔVTH is as small as 0.1 V for a gate voltage swing up to–10 V,which is among the best results reported in the literature.The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN_(x) is a promising approach to improve the device performance of GaN p-MISFET.
基金This work was supported in part by the National Key Research and Development Program of China under Grant 2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences(CAS)+4 种基金in part by CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62074161,Grant 62004213,and Grant U20A20208in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by IMECAS-HKUST-Joint Laboratory of Microelectronics.
文摘In this letter,an enhancement-mode(E-mode)GaN p-channel field-effect transistor(p-FET)with a high current den-sity of−4.9 mA/mm based on a O_(3)-Al_(2)O_(3)/HfO_(2)(5/15 nm)stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure.Attributed to the p++-GaN capping layer,a good linear ohmic I−V characteristic fea-turing a low-contact resistivity(ρc)of 1.34×10^(−4)Ω·cm^(2) was obtained.High gate leakage associated with the HfO_(2)high-k gate dielectric was effectively blocked by the 5-nm O_(3)-Al_(2)O_(3)insertion layer grown by atomic layer deposition,contributing to a high ION/IOFF ratio of 6×10^(6)and a remarkably reduced subthreshold swing(SS)in the fabricated p-FETs.The proposed structure is compelling for energy-efficient GaN complementary logic(CL)circuits.
基金supported in part by the National Key Research and Development Program of China under Grant2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences(CAS)+5 种基金in part by CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62334012,Grant 62074161,Grant 62004213,Grant U20A20208Grant 62304252in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by IMECAS-HKUST-Joint Laboratory of Microelectronics。
文摘In this study,we present the development of self-aligned p-channel Ga N back gate injection transistors(SA-BGITs)that exhibit a high ON-state current.This achievement is primarily attributed to the conductivity modulation effect of the 2-D electron gas(2DEG,the back gate)beneath the 2-D hole gas(2DHG)channel.SA-BGITs with a gate length of 1μm have achieved an impressive peak drain current(I_(D,MAX))of 9.9 m A/mm.The fabricated SA-BGITs also possess a threshold voltage of 0.15 V,an exceptionally minimal threshold hysteresis of 0.2 V,a high switching ratio of 10~7,and a reduced ON-resistance(RON)of 548Ω·mm.Additionally,the SA-BGITs exhibit a steep sub-threshold swing(SS)of 173 mV/dec,further highlighting their suitability for integration into Ga N logic circuits.
基金supported by the Fundamental Research Funds in Xidian Universities (Grant No.JY10000904009)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (Grant No.2007BAK25B03)
文摘Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.
