In this work,we propose a comprehensive theoretical framework for the multilevel NAND(NOT AND logic)flash memory,built upon the modified Student’s t distribution where the distortion of the threshold voltage caused b...In this work,we propose a comprehensive theoretical framework for the multilevel NAND(NOT AND logic)flash memory,built upon the modified Student’s t distribution where the distortion of the threshold voltage caused by the random telegraph noise,cell-to-cell interference and data retention noise are jointly considered.Based on the superposition modulation,we build a non-orthogonal multiuser communication model where a linear mapping is conducted between the verify voltages and binary antipodal symbols.Aimed at improving the storage efficiency,we propose an unequal amplitude mapping(UAM)solution by optimizing the weighting coefficients of verify voltages to intelligently adjust the width of each state.Moreover,the uniform storage efficiency region and sum storage efficiency of different labelings with various decoding schemes are discussed.Simulation results validate the effectiveness of our proposed UAM solution where an up to 20.9%storage efficiency gain can be achieved compared to the current used benchmark scheme.In addition,analytical and simulation results also demonstrate that the successive cancellation decoding outperforms other decoding schemes for all labelings.展开更多
A novel p-channel selected n-channel divided bit-line NOR(PNOR) flash memory,which features low programming current,low power,high access current,and slight bit-line disturbance,is proposed.By using the source induced...A novel p-channel selected n-channel divided bit-line NOR(PNOR) flash memory,which features low programming current,low power,high access current,and slight bit-line disturbance,is proposed.By using the source induced band-to-band hot electron injection (SIBE) to perform programming and dividing the bit-line to the sub-bit-lines,the programming current and power can be reduced to 3.5μA and 16.5μW with the sub-bit-line width equaling to 128,and a read current of 60μA is obtained.Furthermore,the bit-line disturbance is also significantly alleviated.展开更多
A novel band to band hot electron programming flash memory device,which features programming with high speed,low voltage,low power consumption,large read current and short access time,is proposed.The new memory cell...A novel band to band hot electron programming flash memory device,which features programming with high speed,low voltage,low power consumption,large read current and short access time,is proposed.The new memory cell is programmed by band to band tunneling induced hot electron (BBHE) injection method at the drain,and erased by Fowler Nordheim tunneling through the source region.The work shows that the programming control gate voltage can be reduced to 8V,and the drain leakage current is only 3μA/μm.Under the proposed operating conditions,the program efficiency and the read current rise up to 4×10 -4 and 60μA/μm,respectively,and the program time can be as short as 16μs展开更多
A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing....A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.展开更多
Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure ...Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.展开更多
Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,hig...Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...展开更多
Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed ...Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.展开更多
Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/c...Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.展开更多
基金supported by Key Project of Sichuan Provincial Natural Science Foundation(No.2022NSFSC0043).
文摘In this work,we propose a comprehensive theoretical framework for the multilevel NAND(NOT AND logic)flash memory,built upon the modified Student’s t distribution where the distortion of the threshold voltage caused by the random telegraph noise,cell-to-cell interference and data retention noise are jointly considered.Based on the superposition modulation,we build a non-orthogonal multiuser communication model where a linear mapping is conducted between the verify voltages and binary antipodal symbols.Aimed at improving the storage efficiency,we propose an unequal amplitude mapping(UAM)solution by optimizing the weighting coefficients of verify voltages to intelligently adjust the width of each state.Moreover,the uniform storage efficiency region and sum storage efficiency of different labelings with various decoding schemes are discussed.Simulation results validate the effectiveness of our proposed UAM solution where an up to 20.9%storage efficiency gain can be achieved compared to the current used benchmark scheme.In addition,analytical and simulation results also demonstrate that the successive cancellation decoding outperforms other decoding schemes for all labelings.
文摘A novel p-channel selected n-channel divided bit-line NOR(PNOR) flash memory,which features low programming current,low power,high access current,and slight bit-line disturbance,is proposed.By using the source induced band-to-band hot electron injection (SIBE) to perform programming and dividing the bit-line to the sub-bit-lines,the programming current and power can be reduced to 3.5μA and 16.5μW with the sub-bit-line width equaling to 128,and a read current of 60μA is obtained.Furthermore,the bit-line disturbance is also significantly alleviated.
文摘A novel band to band hot electron programming flash memory device,which features programming with high speed,low voltage,low power consumption,large read current and short access time,is proposed.The new memory cell is programmed by band to band tunneling induced hot electron (BBHE) injection method at the drain,and erased by Fowler Nordheim tunneling through the source region.The work shows that the programming control gate voltage can be reduced to 8V,and the drain leakage current is only 3μA/μm.Under the proposed operating conditions,the program efficiency and the read current rise up to 4×10 -4 and 60μA/μm,respectively,and the program time can be as short as 16μs
文摘A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.
文摘Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.
文摘Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...
文摘Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.
基金Project supported by the National Natural Science Foundation of China(Grant No.616340084)the Youth Innovation Promotion Association of CAS(Grant No.2014101)+1 种基金the International Cooperation Project of CASthe Austrian-Chinese Cooperative R&D Projects(Grant No.172511KYSB20150006)
文摘Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.
