A promising technology named epitaxy on nano-scale freestanding fin （ENFF） is firstly proposed for hetero- epitaxy. This technology can effectively release total strain energy and then can reduce the probability of ...A promising technology named epitaxy on nano-scale freestanding fin （ENFF） is firstly proposed for hetero- epitaxy. This technology can effectively release total strain energy and then can reduce the probability of gener- ating mismatch dislocations. Based on the calculation, dislocation defects can be eliminated completely when the thickness of the Si freestanding fin is less than 10nm for the epitaxial Ge layer. In addition, this proposed ENFF process can provide sufficient uniaxial stress for the epitaxy layer, which can be the major stressor for the SiGe or Ge channel fin field-effect transistor or nanowire at the 10nm node and beyond. According to the results of technology computer-aided design simulation, nanowires integrated with ENFF show excellent electrical perfor- mance for uniaxial stress and band offset. The ENFF process is compatible with the state of the art mainstream technology, which has a good potential for future applications.展开更多
Correction to:Nano-Micro Letters(2025)17:191 https://doi.org/10.1007/s40820-025-01702-7 Following the publication of the original article[1],the authors reported an error in Fig.3(b),and the figure legend was reversed...Correction to:Nano-Micro Letters(2025)17:191 https://doi.org/10.1007/s40820-025-01702-7 Following the publication of the original article[1],the authors reported an error in Fig.3(b),and the figure legend was reversed.The correct Fig.3 has been provided in this orrection.展开更多
Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of ...Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.展开更多
According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down tran...This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.展开更多
The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)so...The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)solutions.This study is cen-tered on the optimization of a high-efficiency,low-power"L"-shaped split-gate floating-gate(FG)memory for CIM applications.Fabricated on a 55 nm CMOS platform,the memory devices were systematically investigated through wafer acceptance test(WAT),Sentaurus™simulations and comprehensive evaluations with the DNN+NeuroSim Framework V2.0.Among devices with diverse FG lengths,the 95-nm FG variant exhibits outstanding performance:it achieves a 5.35 V memory window,reaches a maximum conductance of 16.7μS with excellent linearity under the varying voltage and width pulse scheme(VWPS),real-izes 32-state multi-level storage,and attains a 92%training accuracy on the CIFAR-10 dataset using the VGG8 neural network.展开更多
With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not o...With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not only globally,but also locally on every tip of the pad asperities.Conventional diamond disks used for dressing the polyurethane pads cannot produce asperities to achieve such uniformity.A new design of diamond disk was fabricated by casting diamond film on a silicon wafer that contains patterned etching pits. This silicon mold was subsequently removed by dissolution in a hydroxide solution.The diamond film followed the profile of the etching pits on silicon to form pyramids of identical in size and shape.The variation of their tip heights was in microns of single digit that was about one order of magnitude smaller than conventional diamond disks for CMP production.Moreover,the diamond film contained no metal that might contaminate the circuits on polished wafer during a CMP operation.The continuous diamond film could resist any corrosive attack by slurry of acid or base.Consequently,in-situ dressing during CMP is possible that may improve wafer uniformity and production throughput.This ideal diamond disk(IDD) is designed for the future manufacture of advanced semiconductor chips with node sizes of 32 nm or smaller.展开更多
基金Supported by the National Key Research and Development Program of China(2016YFA0301701)the Youth Innovation Promotion Association of CAS under Grant No 2016112
文摘A promising technology named epitaxy on nano-scale freestanding fin （ENFF） is firstly proposed for hetero- epitaxy. This technology can effectively release total strain energy and then can reduce the probability of gener- ating mismatch dislocations. Based on the calculation, dislocation defects can be eliminated completely when the thickness of the Si freestanding fin is less than 10nm for the epitaxial Ge layer. In addition, this proposed ENFF process can provide sufficient uniaxial stress for the epitaxy layer, which can be the major stressor for the SiGe or Ge channel fin field-effect transistor or nanowire at the 10nm node and beyond. According to the results of technology computer-aided design simulation, nanowires integrated with ENFF show excellent electrical perfor- mance for uniaxial stress and band offset. The ENFF process is compatible with the state of the art mainstream technology, which has a good potential for future applications.
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund (L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No. 62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua Universitysponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program
文摘Correction to:Nano-Micro Letters(2025)17:191 https://doi.org/10.1007/s40820-025-01702-7 Following the publication of the original article[1],the authors reported an error in Fig.3(b),and the figure legend was reversed.The correct Fig.3 has been provided in this orrection.
基金supported in part by STI 2030-Major Projects under Grant 2022ZD0209200in part by Beijing Natural Science Foundation-Xiaomi Innovation Joint Fund(L233009)+4 种基金in part by National Natural Science Foundation of China under Grant No.62374099in part by the Tsinghua-Toyota Joint Research Fundin part by the Daikin Tsinghua Union Programin part by Independent Research Program of School of Integrated Circuits,Tsinghua UniversityThis work was also sponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program.
文摘Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness.As the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to rise.The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://irds.ieee.org/),but not publicly confirmed,indicating that more possibilities still exist.The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and speed.In this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and performances.And then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint.Under these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power consumption.This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”nodes.At the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power consumption.Further,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V CPUs.This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
文摘This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.
基金supported by National Key Research and Development Program of China(2022YFF0605803)Zhejiang key R&D project(2023C01017)the Zhejiang Key Research and Development Project(2024SJCZX0030).
文摘The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)solutions.This study is cen-tered on the optimization of a high-efficiency,low-power"L"-shaped split-gate floating-gate(FG)memory for CIM applications.Fabricated on a 55 nm CMOS platform,the memory devices were systematically investigated through wafer acceptance test(WAT),Sentaurus™simulations and comprehensive evaluations with the DNN+NeuroSim Framework V2.0.Among devices with diverse FG lengths,the 95-nm FG variant exhibits outstanding performance:it achieves a 5.35 V memory window,reaches a maximum conductance of 16.7μS with excellent linearity under the varying voltage and width pulse scheme(VWPS),real-izes 32-state multi-level storage,and attains a 92%training accuracy on the CIFAR-10 dataset using the VGG8 neural network.
文摘With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not only globally,but also locally on every tip of the pad asperities.Conventional diamond disks used for dressing the polyurethane pads cannot produce asperities to achieve such uniformity.A new design of diamond disk was fabricated by casting diamond film on a silicon wafer that contains patterned etching pits. This silicon mold was subsequently removed by dissolution in a hydroxide solution.The diamond film followed the profile of the etching pits on silicon to form pyramids of identical in size and shape.The variation of their tip heights was in microns of single digit that was about one order of magnitude smaller than conventional diamond disks for CMP production.Moreover,the diamond film contained no metal that might contaminate the circuits on polished wafer during a CMP operation.The continuous diamond film could resist any corrosive attack by slurry of acid or base.Consequently,in-situ dressing during CMP is possible that may improve wafer uniformity and production throughput.This ideal diamond disk(IDD) is designed for the future manufacture of advanced semiconductor chips with node sizes of 32 nm or smaller.
