Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the tempera...Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.展开更多
Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model wit...Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis, the proposed analytical model has summed up the influence of the configuration of multilevel interconnections, the via heat transfer and self-heating effect on the interconnection delay, which is closer to the actual situation. Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter, which can be applied in nanometer CMOS system chip computer-aided design.展开更多
According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed r...According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance inductance-capacitance （RLC） interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor （CMOS） process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation （EDA） and the design optimization for nanometer CMOS integrated circuits.展开更多
Spin-on-glass （SOG）, an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide （SiO2） depo...Spin-on-glass （SOG）, an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide （SiO2） deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos 60676009 and 60725415)the National High Technology Research and Development Program of China (Grant Nos 2009AA01Z258 and 2009AA01Z260)
文摘Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60971066 and 60725415)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)National Key Laboratory Foundation of China(Grant No. ZHD200904)
文摘Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis, the proposed analytical model has summed up the influence of the configuration of multilevel interconnections, the via heat transfer and self-heating effect on the interconnection delay, which is closer to the actual situation. Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter, which can be applied in nanometer CMOS system chip computer-aided design.
基金supported by the National Natural Science Foundation of China (Grant Nos.60725415 and 60971066)
文摘According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance inductance-capacitance （RLC） interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor （CMOS） process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation （EDA） and the design optimization for nanometer CMOS integrated circuits.
文摘Spin-on-glass （SOG）, an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide （SiO2） deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.
