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A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect 被引量:2

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect
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摘要 Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies. Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2009年第11期4995-5000,共6页 中国物理B(英文版)
基金 Project supported by the National Natural Science Foundation of China (Grant Nos 60676009 and 60725415) the National High Technology Research and Development Program of China (Grant Nos 2009AA01Z258 and 2009AA01Z260)
关键词 multilevel interconnects temperature distribution SELF-HEATING via effect multilevel interconnects, temperature distribution, self-heating, via effect
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