Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback sh...Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.展开更多
为有效提高嵌入式静态随机访问存储器(Static Random Access Memory,SRAM)的可靠性,进而确保整个航天电子系统的可靠运行,通过对嵌入式SRAM故障分布特点的分析,给出了一种改进的存储器架构。采用列块修复与行单元修复相配合的方法,并在...为有效提高嵌入式静态随机访问存储器(Static Random Access Memory,SRAM)的可靠性,进而确保整个航天电子系统的可靠运行,通过对嵌入式SRAM故障分布特点的分析,给出了一种改进的存储器架构。采用列块修复与行单元修复相配合的方法,并在此基础上提出了二维冗余模块存在故障的内建冗余分析(Built-In Re-dundancy Analysis,BIRA)策略。该策略高效运用了设置的行修复寄存器与列修复寄存器,极大地提高了故障的修复率。通过64×8位的SRAM仿真实验验证了提出的内建冗余分析策略的可行性,有效确保了系统在冗余模块和主存储器都存在故障的情况下的高可靠运行。展开更多
基金Fundamental Research Funds for the Central Universities(No.JUSRP51510)Primary Research&Development Plan of Jiangsu Province(No.BE2019003-2)。
文摘Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.
