A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some...A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some proprieties of the interconnect network are found to be redundant and pruned before reduction.For common interconnect networks,the scale of reduced models is smaller than 50% of the scale of previous works.展开更多
A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is im...A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.展开更多
A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transf...A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.展开更多
This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,o...This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.展开更多
Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multipl...Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multiplicative controller gain uncertainties is proposed for realizing the mixed-synchronization of Chua＇s circuits connected in a drive-response configuration. In particular, in the mixed-synchronization regime, different state variables of the response system can evolve into complete synchronization, anti-synchronization and even amplitude death simultaneously with the drive variables for an appropriate choice of scaling matrix. Using Lyapunov stability theory, we derive some sufficient criteria for achieving global mixed-synchronization. It is shown that the desired non-fragile state feedback controller can be constructed by solving a set of linear matrix inequalities （LMIs）. Numerical simulations are also provided to demonstrate the effectiveness of the proposed control approach.展开更多
The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-spee...The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.展开更多
线性雪崩光电二极管(Avalanche photodiode,APD)焦平面红外探测器有着广泛应用场景,APD探测器耦合具有多种模式的读出电路可在有限像元面积内实现多模式探测,提升探测系统集成度。本文设计了一种具有红外热成像模式、门控3D成像模式、...线性雪崩光电二极管(Avalanche photodiode,APD)焦平面红外探测器有着广泛应用场景,APD探测器耦合具有多种模式的读出电路可在有限像元面积内实现多模式探测,提升探测系统集成度。本文设计了一种具有红外热成像模式、门控3D成像模式、激光测距模式和异步激光脉冲探测模式的APD读出电路,四种模式复用输入级电路。通过Krummenacher结构抑制背景辐射影响,扩展了光子飞行时间探测范围;提出一种改进型时刻鉴别电路,通过减小时刻鉴别误差提升距离测量精度。读出电路采用0.18μm 3.3 V CMOS工艺设计,阵列规模128×128、像元中心距30μm,最大电荷容量3.74 Me^(-)。仿真结果表明,激光测距模式,在积分电容13 f F、背景电流1~150 nA条件下,背景电流响应幅值≤1.35 m V,远小于激光响应电流500 nA时280 m V的响应幅值;异步激光脉冲探测模式的幅值灵敏度约110 nA、脉宽灵敏度约4 ns;改进型时刻鉴别电路对于150~500 nA的激光脉冲响应,时刻鉴别误差约4 ns。本文设计的多模式复用APD读出电路具有一定工程应用价值。展开更多
文摘A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some proprieties of the interconnect network are found to be redundant and pruned before reduction.For common interconnect networks,the scale of reduced models is smaller than 50% of the scale of previous works.
基金Acknowledgements： This work is supported by National Natural Science Foundation of China （No. 60673084） and Hunan Provincial Natural Science Foundation of China （No. 06JJ4075）.
文摘A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.
基金Supported by the Key Laboratory of Microsatellites,Chinese Academy of Sciences
文摘A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.
文摘This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.
基金Project supported by the Foundation for Distinguished Young Talents in Higher Education of Guangdong Province of China(Grant No. LYM10074)the Natural Science Foundation of Guangdong Province,China (Grant No. 9451042001004076)
文摘Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multiplicative controller gain uncertainties is proposed for realizing the mixed-synchronization of Chua＇s circuits connected in a drive-response configuration. In particular, in the mixed-synchronization regime, different state variables of the response system can evolve into complete synchronization, anti-synchronization and even amplitude death simultaneously with the drive variables for an appropriate choice of scaling matrix. Using Lyapunov stability theory, we derive some sufficient criteria for achieving global mixed-synchronization. It is shown that the desired non-fragile state feedback controller can be constructed by solving a set of linear matrix inequalities （LMIs）. Numerical simulations are also provided to demonstrate the effectiveness of the proposed control approach.
基金Supported by the National Natural Science Foundation of China
文摘The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.
文摘线性雪崩光电二极管(Avalanche photodiode,APD)焦平面红外探测器有着广泛应用场景,APD探测器耦合具有多种模式的读出电路可在有限像元面积内实现多模式探测,提升探测系统集成度。本文设计了一种具有红外热成像模式、门控3D成像模式、激光测距模式和异步激光脉冲探测模式的APD读出电路,四种模式复用输入级电路。通过Krummenacher结构抑制背景辐射影响,扩展了光子飞行时间探测范围;提出一种改进型时刻鉴别电路,通过减小时刻鉴别误差提升距离测量精度。读出电路采用0.18μm 3.3 V CMOS工艺设计,阵列规模128×128、像元中心距30μm,最大电荷容量3.74 Me^(-)。仿真结果表明,激光测距模式,在积分电容13 f F、背景电流1~150 nA条件下,背景电流响应幅值≤1.35 m V,远小于激光响应电流500 nA时280 m V的响应幅值;异步激光脉冲探测模式的幅值灵敏度约110 nA、脉宽灵敏度约4 ns;改进型时刻鉴别电路对于150~500 nA的激光脉冲响应,时刻鉴别误差约4 ns。本文设计的多模式复用APD读出电路具有一定工程应用价值。
