A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some...A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some proprieties of the interconnect network are found to be redundant and pruned before reduction.For common interconnect networks,the scale of reduced models is smaller than 50% of the scale of previous works.展开更多
A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is im...A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.展开更多
A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transf...A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.展开更多
This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,o...This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.展开更多
Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multipl...Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multiplicative controller gain uncertainties is proposed for realizing the mixed-synchronization of Chua＇s circuits connected in a drive-response configuration. In particular, in the mixed-synchronization regime, different state variables of the response system can evolve into complete synchronization, anti-synchronization and even amplitude death simultaneously with the drive variables for an appropriate choice of scaling matrix. Using Lyapunov stability theory, we derive some sufficient criteria for achieving global mixed-synchronization. It is shown that the desired non-fragile state feedback controller can be constructed by solving a set of linear matrix inequalities （LMIs）. Numerical simulations are also provided to demonstrate the effectiveness of the proposed control approach.展开更多
The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-spee...The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.展开更多
Based on the scheme of damped harmonic oscillator quantization and thermo-field dynamics （TFD）, the quantization of mesoscopic damped double resonance RLC circuit with mutual capacitance-inductance coupling is propo...Based on the scheme of damped harmonic oscillator quantization and thermo-field dynamics （TFD）, the quantization of mesoscopic damped double resonance RLC circuit with mutual capacitance-inductance coupling is proposed. The quantum fluctuations of charge and current of each loop in a squeezed vacuum state are studied in the thermal excitation case. It is shown that the fluctuations not only depend on circuit inherent parameters, but also rely on excitation quantum number and squeezing parameter. Moreover, due to the finite environmental temperature and damped resistance, the fluctuations increase with the temperature rising, and decay with time.展开更多
A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of...A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.展开更多
Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a h...Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.展开更多
Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level perf...Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piece-wise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and verify its performance using measured results.展开更多
At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed i...At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.展开更多
By use of Hopfield model and basis solution of homogeneous linear equations which are established in accordance with consistent state, a practical decision method for the existence of optimal Hopfield model of combina...By use of Hopfield model and basis solution of homogeneous linear equations which are established in accordance with consistent state, a practical decision method for the existence of optimal Hopfield model of combinational circuits is provided. Finally, an example is given.展开更多
文摘A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some proprieties of the interconnect network are found to be redundant and pruned before reduction.For common interconnect networks,the scale of reduced models is smaller than 50% of the scale of previous works.
基金Acknowledgements： This work is supported by National Natural Science Foundation of China （No. 60673084） and Hunan Provincial Natural Science Foundation of China （No. 06JJ4075）.
文摘A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.
基金Supported by the Key Laboratory of Microsatellites,Chinese Academy of Sciences
文摘A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.
文摘This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.
基金Project supported by the Foundation for Distinguished Young Talents in Higher Education of Guangdong Province of China(Grant No. LYM10074)the Natural Science Foundation of Guangdong Province,China (Grant No. 9451042001004076)
文摘Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multiplicative controller gain uncertainties is proposed for realizing the mixed-synchronization of Chua＇s circuits connected in a drive-response configuration. In particular, in the mixed-synchronization regime, different state variables of the response system can evolve into complete synchronization, anti-synchronization and even amplitude death simultaneously with the drive variables for an appropriate choice of scaling matrix. Using Lyapunov stability theory, we derive some sufficient criteria for achieving global mixed-synchronization. It is shown that the desired non-fragile state feedback controller can be constructed by solving a set of linear matrix inequalities （LMIs）. Numerical simulations are also provided to demonstrate the effectiveness of the proposed control approach.
基金Supported by the National Natural Science Foundation of China
文摘The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.
基金Project supported by the Natural Science Foundation of Heze University of Shandong Province, China （Grant No XY05WL01）, the University Experimental Technology Foundation of Shandong Province, China （Grant No S04W138）, the Natural Science Foundation of Shandong Province, China （Grant No Y2004A09） and the National Natural Science Foundation of China （Grant No 10574060）.
文摘Based on the scheme of damped harmonic oscillator quantization and thermo-field dynamics （TFD）, the quantization of mesoscopic damped double resonance RLC circuit with mutual capacitance-inductance coupling is proposed. The quantum fluctuations of charge and current of each loop in a squeezed vacuum state are studied in the thermal excitation case. It is shown that the fluctuations not only depend on circuit inherent parameters, but also rely on excitation quantum number and squeezing parameter. Moreover, due to the finite environmental temperature and damped resistance, the fluctuations increase with the temperature rising, and decay with time.
基金supported partly by National Natural Science Foundation of China(Nos.50637010,51077111)partly by the State Key Laboratory of Electrical Insulation and Power Equipment of Xi'an Jiaotong University of China(EIPE09207)
文摘A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.
基金supported by National Natural Science Foundation of China (Nos. 50637010, 51077111)the State Key Laboratory of Electrical Insulation and Power Equipment of Xi'an Jiaotong University of China (EIPE 09207)
文摘Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.
基金Supported by a Research Grant from The National Science Foundation(CCF:0728996)
文摘Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piece-wise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and verify its performance using measured results.
文摘At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.
基金Sate Education Committee's Doctoral Fund under GRANT 3961403National"Eighth Five-Year"Key Project under GRANT 85-703-02-03
文摘By use of Hopfield model and basis solution of homogeneous linear equations which are established in accordance with consistent state, a practical decision method for the existence of optimal Hopfield model of combinational circuits is provided. Finally, an example is given.
