New low-power Level Shifter (LS) circuit is designed by using sleep transistor with Multi Threshold CMOS (MTCMOS) technique for robust logic voltage shifting from sub-threshold to above- threshold domain. MultiSupply ...New low-power Level Shifter (LS) circuit is designed by using sleep transistor with Multi Threshold CMOS (MTCMOS) technique for robust logic voltage shifting from sub-threshold to above- threshold domain. MultiSupply Voltage Design (MSVD) technique is mainly used for energy and speed in modern system-on-chip. In MSVD, level shifters are required to allow different voltage supply to shift from the lower power supply voltage to the higher power supply voltage. This new low-power level shifter circuit is also used for fast response and low leakage power consumption. This low leakage power consumption can be achieved through insertion of sleep transistor and proper transistors sizing. The proposed design efficiently converts 100 mv input signal into 1 v output signal and achieves the power of 2.56 nW by using 90 nm technology.展开更多
This brief presents an ultra-low voltage single-ended level shifter(LS)with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion.At the ultra-l...This brief presents an ultra-low voltage single-ended level shifter(LS)with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion.At the ultra-low input supply voltages,VDDL,the differential LS circuit will gradually be dysfunctional as the inverter produces limited voltage swings at the output.Some prior works have replaced the inverter with a pass transistor,whose gate is connected to the lower supply voltage,VDDL,to ensure the proper operation of the current mirror in its pull-up network(PUN).This requires the use of the“tie-high”standard cell to prevent gate breakdown in the pass transistor but it is unable to function properly at ultra-supply voltage.To solve this problem,we proposed to connect the pass transistor gate to the input transistor’s drain.The proposed LS circuit and prior single-ended LS circuit works have been fabricated in 55nm CMOS technology and a total of 10 chips for each circuit have been measured.The proposed LS circuit operates with a single input signal with a supply voltage of 100mV at a frequency of 1MHz.With a VDDL of 200mV and VDDH of 1.2V,the measured propagation delay is 182.1ns and the energy per transition(EPT)is around 4.35∼5.44 pJ.It has achieved a 1.08∼2.25×improvement in the Figure of Merit(FoM)than prior multi-supply works and a maximum improvement of 1134×compared to prior single-supply work.The FoM is based on the ratio between propagation delay and level conversion differences,which enables us to understand the circuit’s ability to operate efficiently under wide signal-level conversion.展开更多
A GaN-based E/D mode direct-couple logic 6 transistors SRAM unit and a voltage level shifter were designed and fabricated. E-mode and D-mode A1GaN/GaN HEMTs were integrated in one wafer using fluorine plasma treatment...A GaN-based E/D mode direct-couple logic 6 transistors SRAM unit and a voltage level shifter were designed and fabricated. E-mode and D-mode A1GaN/GaN HEMTs were integrated in one wafer using fluorine plasma treatment and using a moderate A1GaN barrier layer heterojunction structure. The 6 transistors SRAM unit consists of two symmetrical E/D mode inverters and two E-mode switch HEMTs. The output low and high voltage of the SRAM unit are 0.95 and 0.07 V at a voltage supply of 1 V. The voltage level shifter lowers the supply voltage using four Ni-A1GaN Schottky diodes in a series at a positive supply voltage of 6 V and a negative supply voltage of-6 V. By controlling the states of inverter modules of the level shifter in turn, the level shifter offers two channel voltage outputs of-0.5 and-5 V. The flip voltage of the level shifter is 0.76 V. Both the SRAM unit and voltage shifter operate correctly, demonstrating the promising potential for GaN-based E/D mode digital and analog integrated circuits. Several considerations are proposed to avoid the influence of threshold voltage degradation of D-mode and E-mode HEMT on the operation of the circuit.展开更多
文摘New low-power Level Shifter (LS) circuit is designed by using sleep transistor with Multi Threshold CMOS (MTCMOS) technique for robust logic voltage shifting from sub-threshold to above- threshold domain. MultiSupply Voltage Design (MSVD) technique is mainly used for energy and speed in modern system-on-chip. In MSVD, level shifters are required to allow different voltage supply to shift from the lower power supply voltage to the higher power supply voltage. This new low-power level shifter circuit is also used for fast response and low leakage power consumption. This low leakage power consumption can be achieved through insertion of sleep transistor and proper transistors sizing. The proposed design efficiently converts 100 mv input signal into 1 v output signal and achieves the power of 2.56 nW by using 90 nm technology.
基金supported by the National Natural Science Foundation of China under Grant 62434006 and Grant 62350610271.
文摘This brief presents an ultra-low voltage single-ended level shifter(LS)with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion.At the ultra-low input supply voltages,VDDL,the differential LS circuit will gradually be dysfunctional as the inverter produces limited voltage swings at the output.Some prior works have replaced the inverter with a pass transistor,whose gate is connected to the lower supply voltage,VDDL,to ensure the proper operation of the current mirror in its pull-up network(PUN).This requires the use of the“tie-high”standard cell to prevent gate breakdown in the pass transistor but it is unable to function properly at ultra-supply voltage.To solve this problem,we proposed to connect the pass transistor gate to the input transistor’s drain.The proposed LS circuit and prior single-ended LS circuit works have been fabricated in 55nm CMOS technology and a total of 10 chips for each circuit have been measured.The proposed LS circuit operates with a single input signal with a supply voltage of 100mV at a frequency of 1MHz.With a VDDL of 200mV and VDDH of 1.2V,the measured propagation delay is 182.1ns and the energy per transition(EPT)is around 4.35∼5.44 pJ.It has achieved a 1.08∼2.25×improvement in the Figure of Merit(FoM)than prior multi-supply works and a maximum improvement of 1134×compared to prior single-supply work.The FoM is based on the ratio between propagation delay and level conversion differences,which enables us to understand the circuit’s ability to operate efficiently under wide signal-level conversion.
基金Project supported by the National Natural Science Foundation of China(No.61334002)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory(No.ZHD201206)the Program for New Century Excellent Talents in University(No.NCET-12-0915)
文摘A GaN-based E/D mode direct-couple logic 6 transistors SRAM unit and a voltage level shifter were designed and fabricated. E-mode and D-mode A1GaN/GaN HEMTs were integrated in one wafer using fluorine plasma treatment and using a moderate A1GaN barrier layer heterojunction structure. The 6 transistors SRAM unit consists of two symmetrical E/D mode inverters and two E-mode switch HEMTs. The output low and high voltage of the SRAM unit are 0.95 and 0.07 V at a voltage supply of 1 V. The voltage level shifter lowers the supply voltage using four Ni-A1GaN Schottky diodes in a series at a positive supply voltage of 6 V and a negative supply voltage of-6 V. By controlling the states of inverter modules of the level shifter in turn, the level shifter offers two channel voltage outputs of-0.5 and-5 V. The flip voltage of the level shifter is 0.76 V. Both the SRAM unit and voltage shifter operate correctly, demonstrating the promising potential for GaN-based E/D mode digital and analog integrated circuits. Several considerations are proposed to avoid the influence of threshold voltage degradation of D-mode and E-mode HEMT on the operation of the circuit.
