Ultra-low-voltage SRAM is an indispensable component that is increasingly adopted in energyefficient computing systems.However,it comes at the cost of increased sensitivity to soft errors.To address this issue,bit-int...Ultra-low-voltage SRAM is an indispensable component that is increasingly adopted in energyefficient computing systems.However,it comes at the cost of increased sensitivity to soft errors.To address this issue,bit-interleaving SRAM is widely used to mitigate soft errors.But it suffers from half-select disturbance.Previous works address such disturbance by using a dedicated write port or enhanced write assist scheme.However,these works may decrease write margin,induce high cell-level write latency,or incur architecture-level time/timing overhead.In this paper,we develop a high-speed bit-interleaving half-select disturb-free memory with data-aware 10T SRAM.First,we present an isolated and decoupled topology with dedicated write control to improve stability.Second,we present a data-aware write path with enhanced write-ability that effectively reduces the write access time.A 40-nm 4-Kb test chip has been fabricated to validate the optimizations above.Measurement results show that our half-select disturb-free test chip achieves a peak operating frequency of 25 MHz and an energy consumption of 0.168 fJ/bit with a supply voltage of 0.35 V.Compared with the state-of-the-art designs,it has achieved a speed up of 2.72×and an energy saving of 93.8%.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62150710549 and Grant U2441247.
文摘Ultra-low-voltage SRAM is an indispensable component that is increasingly adopted in energyefficient computing systems.However,it comes at the cost of increased sensitivity to soft errors.To address this issue,bit-interleaving SRAM is widely used to mitigate soft errors.But it suffers from half-select disturbance.Previous works address such disturbance by using a dedicated write port or enhanced write assist scheme.However,these works may decrease write margin,induce high cell-level write latency,or incur architecture-level time/timing overhead.In this paper,we develop a high-speed bit-interleaving half-select disturb-free memory with data-aware 10T SRAM.First,we present an isolated and decoupled topology with dedicated write control to improve stability.Second,we present a data-aware write path with enhanced write-ability that effectively reduces the write access time.A 40-nm 4-Kb test chip has been fabricated to validate the optimizations above.Measurement results show that our half-select disturb-free test chip achieves a peak operating frequency of 25 MHz and an energy consumption of 0.168 fJ/bit with a supply voltage of 0.35 V.Compared with the state-of-the-art designs,it has achieved a speed up of 2.72×and an energy saving of 93.8%.
文摘以榆林国家樟子松良种基地樟子松优树子代测定林半同胞家系为研究材料,测定树高、胸径、材积等生长数据,进行方差分析和各性状间的相关性分析,估算遗传力、变异系数、遗传增益、育种值等遗传参数。树高的家系平均值为4.89 m,胸径的家系平均值为10.82 cm,材积的家系平均值为0.0248 m 3,不同家系间的生长表现存在较大的差异。树高、胸径、材积3个生长性状在不同家系均存在极显著差异,3个性状在不同家系间存在丰富的遗传变异。树高、胸径、材积的单株遗传力分别为0.687、0.587、0.571,家系遗传力分别为为0.729、0.697、0.684,树高、胸径、材积的遗传变异系数分别为22.25%、21.89%、35.97%,各性状的遗传力和遗传变异系数均较大。以家系材积育种值为家系选择指标,以70%的入选率选出较为优良的36个家系,在每一个家系内选出单株材积最大者为第二代种子园建园亲本。
