In metal-gate/high-k stacks adopted by the 45 nm technology node, the fiat-band voltage （Vfb） shift remains one of the most critical challenges, particularly the flat-band voltage roll-off （Vfb roll-off） phenomeno...In metal-gate/high-k stacks adopted by the 45 nm technology node, the fiat-band voltage （Vfb） shift remains one of the most critical challenges, particularly the flat-band voltage roll-off （Vfb roll-off） phenomenon in p-channel metal- oxide-semiconductor （pMOS） devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the Vfb shift and the origin of the Vfb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the Vfb shift phenomenon are summarized and the future research trend is described.展开更多
In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering...In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.展开更多
This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent o...This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.展开更多
A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS c...A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.展开更多
A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/...A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.展开更多
Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the ...Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density （JL） of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.展开更多
The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because...The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.展开更多
With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investig...With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.展开更多
The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-spee...The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.展开更多
Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the variou...Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.展开更多
The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the ...The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.展开更多
By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect ...By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.展开更多
The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain ...The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.展开更多
We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overl...We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.展开更多
The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,i...The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.展开更多
A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. ...A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.展开更多
High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to ...High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.展开更多
Gadolinium oxide(Gd2O3) film has potential as a candidate gate dielectric to replace Hf O2. In this work,we provide a simple method by trace Ta(~1%) doping to significantly improve the dielectric properties of Gd2O3 f...Gadolinium oxide(Gd2O3) film has potential as a candidate gate dielectric to replace Hf O2. In this work,we provide a simple method by trace Ta(~1%) doping to significantly improve the dielectric properties of Gd2O3 film. And effects of annealing temperatures of Ta-doped Gd2O3(GTO) films are investigated in detail. Results show that GTO film annealed at 500℃ exhibits excellent performance as a novel gate dielectric material for integrated circuit, showing a small surface roughness of 0.199 nm, a large band gap of 5.45 e V, a high dielectric constant(k) of 21.2 and a low leakage current density(Jg) of 2.10 × 10^-3A/cm^2.All properties of GTO films are superior to pure Gd2O3 films and these GTO films meet the requirements for next-generation gate dielectrics. In addition, impedance spectrum is first used to analyze the equivalent circuit of GTO based metal-oxide-semiconductor(MOS) capacitors, which represents a new insight to understand observed electrical behaviors.展开更多
A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structur...A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.展开更多
基金Project supported by the National Natural Science Foundation of China (Grants Nos.50802005 and 11074020)the Program for New Century Excellent Talents in University,China (Grant No.NCET-08-0029)+1 种基金the Ph.D.Program Foundation of Ministry of Education of China (Grant No.200800061055)the Hong Kong Research Grants Council General Research Funds,China (Grant No.CityU112608)
文摘In metal-gate/high-k stacks adopted by the 45 nm technology node, the fiat-band voltage （Vfb） shift remains one of the most critical challenges, particularly the flat-band voltage roll-off （Vfb roll-off） phenomenon in p-channel metal- oxide-semiconductor （pMOS） devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the Vfb shift and the origin of the Vfb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the Vfb shift phenomenon are summarized and the future research trend is described.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China (Grant No. 708083)the Fundamental Research Funds for the Central Universities (Grant No. 20110203110012)
文摘In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.
基金supported by the State Key Development Program for Basic Research of China (Grant No 2006CB302704)the National Natural Science Foundation of China (Grant No 60776030)
文摘This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00607)the National Natural Science Foundation of China(Grant Nos.61106089 and 61376097)the Zhejiang Provincial Natural Science Foundation of China(Grant No.LR14F040001)
文摘A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.
基金supported by the National Natural Science of China(Grant Nos.61176091 and 50932001)
文摘A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.
基金General Research Institute for Nonferrous Metals Research Fund (82262)
文摘Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density （JL） of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.
基金support from Natural Science Foundation of Jiangsu Province (ProjectNo. BK2007130)National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010)+3 种基金Ministry of Science and Technology of China (Grant No.2009CB929503)Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and2009ZX02101-4)the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education MinistryNational Found for Fostering Talents of Basic Science (NFFTBS) (ProjectNo. J0630316)
文摘The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.
基金the support from the National Major Project of Fundamental Research:Nanomaterials and Nanostructures(Grant No.2005CB623603)the National Natural Science Foundation of China(Grant No.10674138)the Special Fund for President Scholarship,Chinese Academy of Sciences.
文摘With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.
基金Supported by the National Natural Science Foundation of China
文摘The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.
基金supported by the National Natural Science Foundation of China(51172009,51172013 and 11074020)Program for New Century Excellent Talents in University(NCET-08-0029)+1 种基金Hong Kong Research Grants Council(RGC)General Research Funds(GRF)(CityU112510)City University of Hong Kong Strategic Research Grant(SRG)(7008009)
文摘Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.2015AA010601)
文摘The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.
基金supported by the Fundamental Research Funds for the Central Universities (Grant No. K50511250001)the National Natural Science Foundation of China (Grant No. 61076101)
文摘By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project of Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities,China(Grant No.20110203110012)
文摘The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities of China(Grant No.20110203110012)
文摘We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Micro Electronics of Chinese Academy of Sciences
文摘The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Micro Electronics of Chinese Academy of Sciences
文摘High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.
基金supported financially by the Project of Ministry of Science and Technology of the People’s Republic of China (No. 2017YFB0405902)the National Natural Science Foundation of China (Nos. 51431001, 51771002, 21771006, U1607126 and 21621061)Beijing Municipal Commission of Science and Technology (No. Z17110000091702)
文摘Gadolinium oxide(Gd2O3) film has potential as a candidate gate dielectric to replace Hf O2. In this work,we provide a simple method by trace Ta(~1%) doping to significantly improve the dielectric properties of Gd2O3 film. And effects of annealing temperatures of Ta-doped Gd2O3(GTO) films are investigated in detail. Results show that GTO film annealed at 500℃ exhibits excellent performance as a novel gate dielectric material for integrated circuit, showing a small surface roughness of 0.199 nm, a large band gap of 5.45 e V, a high dielectric constant(k) of 21.2 and a low leakage current density(Jg) of 2.10 × 10^-3A/cm^2.All properties of GTO films are superior to pure Gd2O3 films and these GTO films meet the requirements for next-generation gate dielectrics. In addition, impedance spectrum is first used to analyze the equivalent circuit of GTO based metal-oxide-semiconductor(MOS) capacitors, which represents a new insight to understand observed electrical behaviors.
基金Project supported by“Efficient and Energy-Saving GaN on Si Power Devices”Research Fund(Grant No.KQCX20140522151322946)the Research Fund of the Third Generation Semiconductor Key Laboratory of Shenzhen,China(Grant No.ZDSYS20140509142721434)+1 种基金the“Key Technology Research of GaN on Si Power Devices”Research Fund(Grant No.JSGG20140729145956266)the“Research of Low Cost Fabrication of GaN Power Devices and System Integration”Research Fund(Grant No.JCYJ201602261926390)
文摘A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.
