Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most...Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.展开更多
The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom...The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.展开更多
On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology wa...On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.展开更多
The current milieu,encourages rapid growth of wireless communication,multimedia applications,robotics and graphics to have efficient utilization of resources with high throughput and low power digital signal processin...The current milieu,encourages rapid growth of wireless communication,multimedia applications,robotics and graphics to have efficient utilization of resources with high throughput and low power digital signal processing(DSP)systems.In an aggregate DSP system ranging from audio/video signal processing to wireless sensor networks,floating point matrix multiplication is used in wide scale in most of the fundamental processing units.Hardware implementation of floating-point matrix multiplication demands a colossal number of arithmetic operations that alter speed and consuming more area and power.DSP systems essentially uses two techniques to reduce dynamic power consumption:-they are pipelining and parallel processing that needs high performance processing element with less area and low power in diverse scientific computing applications.However,number of adders and multipliers used in the design of floating-point unit also increases subsequently.The adders and multipliers are the most area,delay and power consuming data path elements in the processing unit.The arithmetic level reduction of delay,power and area in the processing element is performed by the selection of appropriate adders and multipliers.This article proposes a parallel multiplication architecture using Strassen and UrdhvaTiryagbhyam multiplier,which involves design of efficient parallel matrix multiplication with flexible implementation of FPGA(Field Programmable Gate Array)device to analyse the computation and area.The design incorporates scheduling of blocks,operations on processing elements,block size determination,parallelization and double buffering for storage of matrix elements.展开更多
文摘Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.
文摘The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.
文摘On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.
基金funded by the research general direction at Universidad Santiago de Cali,Colombia under call no 01-2022.
文摘The current milieu,encourages rapid growth of wireless communication,multimedia applications,robotics and graphics to have efficient utilization of resources with high throughput and low power digital signal processing(DSP)systems.In an aggregate DSP system ranging from audio/video signal processing to wireless sensor networks,floating point matrix multiplication is used in wide scale in most of the fundamental processing units.Hardware implementation of floating-point matrix multiplication demands a colossal number of arithmetic operations that alter speed and consuming more area and power.DSP systems essentially uses two techniques to reduce dynamic power consumption:-they are pipelining and parallel processing that needs high performance processing element with less area and low power in diverse scientific computing applications.However,number of adders and multipliers used in the design of floating-point unit also increases subsequently.The adders and multipliers are the most area,delay and power consuming data path elements in the processing unit.The arithmetic level reduction of delay,power and area in the processing element is performed by the selection of appropriate adders and multipliers.This article proposes a parallel multiplication architecture using Strassen and UrdhvaTiryagbhyam multiplier,which involves design of efficient parallel matrix multiplication with flexible implementation of FPGA(Field Programmable Gate Array)device to analyse the computation and area.The design incorporates scheduling of blocks,operations on processing elements,block size determination,parallelization and double buffering for storage of matrix elements.
