摘要
The current milieu,encourages rapid growth of wireless communication,multimedia applications,robotics and graphics to have efficient utilization of resources with high throughput and low power digital signal processing(DSP)systems.In an aggregate DSP system ranging from audio/video signal processing to wireless sensor networks,floating point matrix multiplication is used in wide scale in most of the fundamental processing units.Hardware implementation of floating-point matrix multiplication demands a colossal number of arithmetic operations that alter speed and consuming more area and power.DSP systems essentially uses two techniques to reduce dynamic power consumption:-they are pipelining and parallel processing that needs high performance processing element with less area and low power in diverse scientific computing applications.However,number of adders and multipliers used in the design of floating-point unit also increases subsequently.The adders and multipliers are the most area,delay and power consuming data path elements in the processing unit.The arithmetic level reduction of delay,power and area in the processing element is performed by the selection of appropriate adders and multipliers.This article proposes a parallel multiplication architecture using Strassen and UrdhvaTiryagbhyam multiplier,which involves design of efficient parallel matrix multiplication with flexible implementation of FPGA(Field Programmable Gate Array)device to analyse the computation and area.The design incorporates scheduling of blocks,operations on processing elements,block size determination,parallelization and double buffering for storage of matrix elements.
基金
funded by the research general direction at Universidad Santiago de Cali,Colombia under call no 01-2022.
