A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by...A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.展开更多
A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expres...A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.展开更多
A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derive...A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.展开更多
The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor （DG ASiNR FET） are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium G...The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor （DG ASiNR FET） are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green＇s function （NEGF） approach self-consistently coupled with a three-dimensional （3D） Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain mag- nitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power （GMP） is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.展开更多
As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for devic...As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.展开更多
This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a p...This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.展开更多
This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potenti...This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.展开更多
The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface...The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.展开更多
A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performan...A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.展开更多
In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxi...In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.展开更多
In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T D...In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.展开更多
A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson＇s equation to obtain the relationship between the surface potential and voltage in the channel region in a self-...A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson＇s equation to obtain the relationship between the surface potential and voltage in the channel region in a self-consistent way. The drain current expression is then obtained from Pao-Sah＇s double integral. The model consists of one set of surface potential equations,and the analytic drain current can be evaluated from the surface potential at the source and drain ends. It is demonstrated that the model is valid for all operation regions of the double-gate MOSFETs and without any need for simplification （e. g., by using the charge sheet assumption） or auxiliary fitting functions. The model has been verified by extensive comparisons with 2D numerical simulation under different operation conditions with different geometries. The consistency between the model calculation and numerical simulation demonstrates the accuracy of the model.展开更多
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI...A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.展开更多
We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope i...We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.展开更多
A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poi...A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.展开更多
On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a thresho...On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.展开更多
A model of subthreshold characteristics for both undoped and doped double-gate （DG） MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson＇s equation using variable separa- tion techn...A model of subthreshold characteristics for both undoped and doped double-gate （DG） MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson＇s equation using variable separa- tion technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thick- ness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations＇ results and found very good agreement.展开更多
A novel device structure with a vertical double-gate and dual-strained channel is presented.The electrical characteristics of this device with a gate length of 100 nm are simulated.With a Ge content of 20%,the drain c...A novel device structure with a vertical double-gate and dual-strained channel is presented.The electrical characteristics of this device with a gate length of 100 nm are simulated.With a Ge content of 20%,the drain currents of the strained-Si NMOSFET and the strained-SiGe PMOSFET compared to the universal SOI MOSFETs are enhanced by 26% and 33%,respectively;the risetime and the falltime of the strained-channel CMOS are greatly decreased by 50% and 25.47% compared to their traditional Si channel counterparts.The simulation results show that the vertical double-gate（DG） dual-strained-channel MOSFETs exhibit better drive capability,a higher transconductance,and a faster circuit speed for CMOS compared to conventional-Si MOSFETs.The new structure can be achieved by today＇s semiconductor manufacturing level.展开更多
A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both expone...A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminatestheregionalapproach.Modelpredictionsarecomparedtonumericalsimulationswithcloseagreement,having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.展开更多
A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potentia...A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.展开更多
文摘A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.
文摘A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.
基金Project supported by the National Natural Science Foundation of China(Grant No.60876027)the Open Funds of Jiangsu Province Key Lab of ASIC Design(JSICK1007)
文摘A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.
文摘The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor （DG ASiNR FET） are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green＇s function （NEGF） approach self-consistently coupled with a three-dimensional （3D） Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain mag- nitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power （GMP） is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.
基金Project supported by the National Natural Science Foundation of China (Grant No.60876027)the National Science Foundation for Distinguished Young Scholars of China (Grant No.60925015)+1 种基金the National Basic Research Program of China (Grant No.2011CBA00600)the Fundamental Research Project of Shenzhen Science & Technology Foundation,China (Grant No.JC200903160353A)
文摘As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.
基金supported by Women Scientist Scheme-A, Department of Science and Technology, New Delhi, Government of India, under the Grant SR/WOS-A/ET-5/2017
文摘This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60976068and60936005)the Cultivation Fund of the Major Science and Technology Innovation,Ministry of Education,China(Grant No.708083)+1 种基金Specialized Research Fund for the Doctoral Program of Higher Education(Grant No.200807010010)the Fundamental Research Funds for the Central Universities
文摘This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376099,11235008,and 61205003)
文摘The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.
基金Project supported by the National Natural Science Foundation of China (Grant No 60625403)the Special Funds for MajorState Basic Research (973) Projects and NCET program
文摘A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.
文摘In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.
文摘In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.
基金the National Natural Science Foundation of China(No.90607017)the Competitive Ear marked Grant 611207 from the Research Grant Council of Hong Kong SARthe International Joint Research Program(NEDO Grant)from Japan(No.NEDOO5/06.EG01)~~
文摘A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson＇s equation to obtain the relationship between the surface potential and voltage in the channel region in a self-consistent way. The drain current expression is then obtained from Pao-Sah＇s double integral. The model consists of one set of surface potential equations,and the analytic drain current can be evaluated from the surface potential at the source and drain ends. It is demonstrated that the model is valid for all operation regions of the double-gate MOSFETs and without any need for simplification （e. g., by using the charge sheet assumption） or auxiliary fitting functions. The model has been verified by extensive comparisons with 2D numerical simulation under different operation conditions with different geometries. The consistency between the model calculation and numerical simulation demonstrates the accuracy of the model.
文摘A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.
基金supported by the Fund ofLiaoning Province Education Department(No.L2012028)
文摘We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.
基金Project supported by the National Natural Science Foundation of China(No.61376106)the Graduate Innovation Fund of Anhui University
文摘A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
基金Project supported by the National Natural Science Foundation of China(Nos60976068,60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(No708083)the Specialized Research Fund for the Doctoral Program of Higher Education(No200807010010)
文摘On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.
基金Project supported by the Fund of Liaoning Province Education Department(No.L2012028)
文摘A model of subthreshold characteristics for both undoped and doped double-gate （DG） MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson＇s equation using variable separa- tion technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thick- ness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations＇ results and found very good agreement.
基金supported by the (Xi’an) Innovation Foundation for Applied Materials of USA (No.XA-AM-2008070) the Education Bureau of Shannxi Province (No. 08JK384)
文摘A novel device structure with a vertical double-gate and dual-strained channel is presented.The electrical characteristics of this device with a gate length of 100 nm are simulated.With a Ge content of 20%,the drain currents of the strained-Si NMOSFET and the strained-SiGe PMOSFET compared to the universal SOI MOSFETs are enhanced by 26% and 33%,respectively;the risetime and the falltime of the strained-channel CMOS are greatly decreased by 50% and 25.47% compared to their traditional Si channel counterparts.The simulation results show that the vertical double-gate（DG） dual-strained-channel MOSFETs exhibit better drive capability,a higher transconductance,and a faster circuit speed for CMOS compared to conventional-Si MOSFETs.The new structure can be achieved by today＇s semiconductor manufacturing level.
基金Project supported by the National Natural Science Foundation of China(No.61204100)the Guangdong Natural Science Foundation(No.S2013010013088)
文摘A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminatestheregionalapproach.Modelpredictionsarecomparedtonumericalsimulationswithcloseagreement,having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.
基金Project supported by the National Natural Science Foundation of China(No.61376106)the University Natural Science Research Key Project of Anhui Province(No.KJ2016A169)the Introduced Talents Project of Anhui Science and Technology University
文摘A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.
