This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary ...This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.展开更多
With the arrival of the big data era, the modern higher education model has undergone radical changes, and higher requirements have been put forward for the data literacy of college teachers. The paper first analyzes ...With the arrival of the big data era, the modern higher education model has undergone radical changes, and higher requirements have been put forward for the data literacy of college teachers. The paper first analyzes the connotation of teacher data literacy, and then combs through the status quo and dilemmas of teachers’ data literacy ability in applied universities. The paper proposes to enhance the data literacy ability of teachers from the perspective of organizational learning. Through building a digital culture, building a data-driven teaching environment, and constructing an interdisciplinary learning community to further promote the application of the theory and practice of datafication inside and outside the organization, and ultimately improve the quality of teaching.展开更多
Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,m...Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.展开更多
An algorithm named DPP is addressed.In it,a new model based on the concept of irregularity degree is founded to evaluate the regularity of cells.It generates the structure regularity of cells by exploiting the signal ...An algorithm named DPP is addressed.In it,a new model based on the concept of irregularity degree is founded to evaluate the regularity of cells.It generates the structure regularity of cells by exploiting the signal flow of circuit.Then,it converts the bit slice structure to parallel constraints to enable Q place algorithm.The design flow and the main algorithms are introduced.Finally,the satisfied experimental result of the tool compared with the Cadence placement tool SE is discussed.展开更多
The radar ray path equations are used to determine the physical location of each radar measurement. These equations are necessary for mapping radar data to computational grids for diagnosis, display and numerical weat...The radar ray path equations are used to determine the physical location of each radar measurement. These equations are necessary for mapping radar data to computational grids for diagnosis, display and numerical weather prediction （NWP）. They are also used to determine the forward operators for assimilation of radar data into forecast models. In this paper, a stepwise ray tracing method is developed. The influence of the atmospheric refractive index on the ray path equations at different locations related to an intense cold front is examined against the ray path derived from the new tracing method. It is shown that the radar ray path is not very sensitive to sharp vertical gradients of refractive index caused by the strong temperature inversion and large moisture gradient in this case. In the paper, the errors caused by using the simplified straight ray path equations are also examined. It is found that there will be significant errors in the physical location of radar measurements if the earth＇s curvature is not considered, especially at lower elevation angles. A reduced form of the equation for beam height calculation is derived using Taylor series expansion. It is computationally more efficient and also avoids the need to use double precision variables to mitigate the small difference between two large terms in the original form. The accuracy of this reduced form is found to be sufficient for modeling use.展开更多
Many ＂rich - connected＂ topologies with multiple parallel paths between smwers have been proposed for data center networks recently to provide high bisection bandwidth, but it re mains challenging to fully utilize t...Many ＂rich - connected＂ topologies with multiple parallel paths between smwers have been proposed for data center networks recently to provide high bisection bandwidth, but it re mains challenging to fully utilize the high network capacity by appropriate multi- path routing algorithms. As flow-level path splitting may lead to trafl＇ic imbalance between paths due to flow- size difference, packet-level path splitting attracts more attention lately, which spreads packets from flows into multiple available paths and significantly improves link utilizations. However, it may cause packet reordering, confusing the TCP congestion control algorithm and lowering the throughput of flows. In this paper, we design a novel packetlevel multi-path routing scheme called SOPA, which leverag- es OpenFlow to perform packet-level path splitting in a round- robin fashion, and hence significantly mitigates the packet reordering problem and improves the network throughput. Moreover, SOPA leverages the topological feature of data center networks to encode a very small number of switches along the path into the packet header, resulting in very light overhead. Compared with random packet spraying （RPS）, Hedera and equal-cost multi-path routing （ECMP）, our simulations demonstrate that SOPA achieves 29.87%, 50.41% and 77.74% higher network throughput respectively under permutation workload, and reduces average data transfer completion time by 53.65%, 343.31% and 348.25% respectively under production workload.展开更多
文摘This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.
文摘With the arrival of the big data era, the modern higher education model has undergone radical changes, and higher requirements have been put forward for the data literacy of college teachers. The paper first analyzes the connotation of teacher data literacy, and then combs through the status quo and dilemmas of teachers’ data literacy ability in applied universities. The paper proposes to enhance the data literacy ability of teachers from the perspective of organizational learning. Through building a digital culture, building a data-driven teaching environment, and constructing an interdisciplinary learning community to further promote the application of the theory and practice of datafication inside and outside the organization, and ultimately improve the quality of teaching.
文摘Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.
文摘An algorithm named DPP is addressed.In it,a new model based on the concept of irregularity degree is founded to evaluate the regularity of cells.It generates the structure regularity of cells by exploiting the signal flow of circuit.Then,it converts the bit slice structure to parallel constraints to enable Q place algorithm.The design flow and the main algorithms are introduced.Finally,the satisfied experimental result of the tool compared with the Cadence placement tool SE is discussed.
基金This work was supported by US NSF ATM-0129892,ATM-0331756,ATM-0331594 and EEC-0313747,and D0T-FAA grant NA17RJ1227-01The first author was also partly supported by the National Natural Science Foundation of China for young investigators(Grant No.40505022)+1 种基金Ming Xue was also supported by the 0utstanding 0verseas Scholars Award of the Chinese Academy of Sciences(Grant No.2004-2-7)Graphic plots were generated by the GNUPL0T graphics package.
文摘The radar ray path equations are used to determine the physical location of each radar measurement. These equations are necessary for mapping radar data to computational grids for diagnosis, display and numerical weather prediction （NWP）. They are also used to determine the forward operators for assimilation of radar data into forecast models. In this paper, a stepwise ray tracing method is developed. The influence of the atmospheric refractive index on the ray path equations at different locations related to an intense cold front is examined against the ray path derived from the new tracing method. It is shown that the radar ray path is not very sensitive to sharp vertical gradients of refractive index caused by the strong temperature inversion and large moisture gradient in this case. In the paper, the errors caused by using the simplified straight ray path equations are also examined. It is found that there will be significant errors in the physical location of radar measurements if the earth＇s curvature is not considered, especially at lower elevation angles. A reduced form of the equation for beam height calculation is derived using Taylor series expansion. It is computationally more efficient and also avoids the need to use double precision variables to mitigate the small difference between two large terms in the original form. The accuracy of this reduced form is found to be sufficient for modeling use.
基金supported by the National Basic Research Program of China(973 program)under Grant No.2014CB347800 and No.2012CB315803the National High-Tech R&D Program of China(863 program)under Grant No.2013AA013303+1 种基金the Natural Science Foundation of China under Grant No.61170291,No.61133006,and No.61161140454ZTE IndustryAcademia-Research Cooperation Funds
文摘Many ＂rich - connected＂ topologies with multiple parallel paths between smwers have been proposed for data center networks recently to provide high bisection bandwidth, but it re mains challenging to fully utilize the high network capacity by appropriate multi- path routing algorithms. As flow-level path splitting may lead to trafl＇ic imbalance between paths due to flow- size difference, packet-level path splitting attracts more attention lately, which spreads packets from flows into multiple available paths and significantly improves link utilizations. However, it may cause packet reordering, confusing the TCP congestion control algorithm and lowering the throughput of flows. In this paper, we design a novel packetlevel multi-path routing scheme called SOPA, which leverag- es OpenFlow to perform packet-level path splitting in a round- robin fashion, and hence significantly mitigates the packet reordering problem and improves the network throughput. Moreover, SOPA leverages the topological feature of data center networks to encode a very small number of switches along the path into the packet header, resulting in very light overhead. Compared with random packet spraying （RPS）, Hedera and equal-cost multi-path routing （ECMP）, our simulations demonstrate that SOPA achieves 29.87%, 50.41% and 77.74% higher network throughput respectively under permutation workload, and reduces average data transfer completion time by 53.65%, 343.31% and 348.25% respectively under production workload.
