First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked...First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the deriv...Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.展开更多
A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic...Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.展开更多
The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and a...The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.展开更多
With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledg...With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.展开更多
Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The ...Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.展开更多
随着超大规模集成电路(Very Large Scale Integration Circuit,VLSI)制造工艺的快速发展以及其对应集成度的不断提高,数字集成电路的设计迎来了许多挑战。时钟树综合是数字后端设计的重要部分,现有的时钟树综合算法开始面临迭代效率变...随着超大规模集成电路(Very Large Scale Integration Circuit,VLSI)制造工艺的快速发展以及其对应集成度的不断提高,数字集成电路的设计迎来了许多挑战。时钟树综合是数字后端设计的重要部分,现有的时钟树综合算法开始面临迭代效率变低和收敛速度变慢的问题。因此,提出了一种同步并发时钟树分级聚类算法(Synchronous Clock-tree Hierarchical Partitioning and Clustering,SC-HPC)。从系统优化的角度出发,SC-HPC将原始的寄存器聚类过程转化为粗聚类和细聚类两步。粗聚类将布局完成的寄存器分为N大簇群,进一步把N个簇的细化任务分配给用户可调度的线程中进行加速处理。细聚类是根据缓冲器最大扇出的规则进行更加细致地划分寄存器。实验结果表明,相较于现有方法,SC-HPC算法降低了缓冲器数量(30%以上)和程序运行时长(20%以上)。展开更多
抑郁症作为一种高致残性精神疾病,其核心病理环节涉及生物钟基因[如时钟基因(circadian locomotor output cycles kaput,CLOCK)、脑和肌肉芳烃受体核转位蛋白1(brain and muscle ARNT-like protein 1,BMAL1)、周期基因(period,PER)和隐...抑郁症作为一种高致残性精神疾病,其核心病理环节涉及生物钟基因[如时钟基因(circadian locomotor output cycles kaput,CLOCK)、脑和肌肉芳烃受体核转位蛋白1(brain and muscle ARNT-like protein 1,BMAL1)、周期基因(period,PER)和隐花色素基因(cryptochrome,CRY)]的表观遗传调控紊乱(DNA甲基化、组蛋白修饰及非编码RNA)。这种失调导致基因表达节律异常,进而引发神经递质失衡、下丘脑-垂体-肾上腺(hypothalamic-pituitaryadrenal,HPA)轴过度激活及神经炎症加剧。基于此,本文提出了“表观-生物钟-神经环路”交互模型,强调视交叉上核(suprachiasmatic nucleus,SCN)主时钟对下丘脑-海马-前额叶环路同步性的调控失能是情绪-认知共病的核心机制。深入研究发现,抑郁症的核心症状及共病受特定生物钟表观调控机制的支配,与癫痫、痴呆等疾病相比,抑郁症具有独特的生物钟表观特征,这揭示了抑郁症与其他疾病共性机制与特异性的区别。动物模型与临床证据的一致性也印证了生物钟表观遗传在抑郁症中的关键作用。针对此机制,治疗策略呈现多元化,包括抗抑郁药物、小分子抑制剂、环境行为干预及基因编辑与RNA疗法,结合生物标志物开发推动精准分型与个性化医疗。抑郁症治疗正基于共性基础向个性化进阶,未来突破方向需聚焦于新型靶点与技术。尽管面临诸多挑战与争议,但该领域从基础到临床的突破性研究为抑郁症诊疗开辟了新路径,有望推动精神疾病进入生物钟医学的新纪元。展开更多
时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据...时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据缓冲与修正处理模块构成。系统采样输出数据通过上传到上位机进行显示与性能指标分析。测试结果表明,该TIADC系统通过对失配误差的数字后端补偿后能稳定工作在1 GS/s采样率。其采样有效位与平均信噪比分别达到7.03 bit与44.1 d B,可以应用于采样失配修正方法的验证与评估。展开更多
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
基金Supported by the NSF of China (# 69773034) and DARPA under contract # F33615-95-C-1627
文摘Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
基金supported by the National Natural Science Foundation of China(61401204)the Fundamental Research Funds for the Central Universities(30916011319)+1 种基金the Technology Research and Development Program of Jiangsu Province(BY2015004-03)the Postdoctoral Science Foundation of Jiangsu Province(1501104C)
文摘Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.
基金Supported by National Natural Science Foundation of Zhejiang Province
文摘The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.
文摘With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.
文摘Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.
文摘随着超大规模集成电路(Very Large Scale Integration Circuit,VLSI)制造工艺的快速发展以及其对应集成度的不断提高,数字集成电路的设计迎来了许多挑战。时钟树综合是数字后端设计的重要部分,现有的时钟树综合算法开始面临迭代效率变低和收敛速度变慢的问题。因此,提出了一种同步并发时钟树分级聚类算法(Synchronous Clock-tree Hierarchical Partitioning and Clustering,SC-HPC)。从系统优化的角度出发,SC-HPC将原始的寄存器聚类过程转化为粗聚类和细聚类两步。粗聚类将布局完成的寄存器分为N大簇群,进一步把N个簇的细化任务分配给用户可调度的线程中进行加速处理。细聚类是根据缓冲器最大扇出的规则进行更加细致地划分寄存器。实验结果表明,相较于现有方法,SC-HPC算法降低了缓冲器数量(30%以上)和程序运行时长(20%以上)。
文摘时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据缓冲与修正处理模块构成。系统采样输出数据通过上传到上位机进行显示与性能指标分析。测试结果表明,该TIADC系统通过对失配误差的数字后端补偿后能稳定工作在1 GS/s采样率。其采样有效位与平均信噪比分别达到7.03 bit与44.1 d B,可以应用于采样失配修正方法的验证与评估。
