A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stabili...A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.展开更多
为提高大电流低压差线性稳压器(Low-Dropout Linear Regulator,LDO)在全负载范围内的稳定性,提出了一种利用负载追踪补偿的LDO电路。该电路采用改进型动态零点补偿技术和阻抗衰减技术,分别实现了零点追踪和极点追踪,同时利用电流缓冲补...为提高大电流低压差线性稳压器(Low-Dropout Linear Regulator,LDO)在全负载范围内的稳定性,提出了一种利用负载追踪补偿的LDO电路。该电路采用改进型动态零点补偿技术和阻抗衰减技术,分别实现了零点追踪和极点追踪,同时利用电流缓冲补偿解决了Miller补偿导致的右平面零点问题,使得稳压器可以在宽负载电流范围下稳定工作。电路采用0.18μm BCD工艺进行设计,仿真结果表明,所设计的LDO电路静态电流为56.3μA,在空载情况下的相位裕度为52°,3 A满载时相位裕度达到85°,在全负载范围内均具有良好的稳定性。展开更多
文摘A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.
文摘为提高大电流低压差线性稳压器(Low-Dropout Linear Regulator,LDO)在全负载范围内的稳定性,提出了一种利用负载追踪补偿的LDO电路。该电路采用改进型动态零点补偿技术和阻抗衰减技术,分别实现了零点追踪和极点追踪,同时利用电流缓冲补偿解决了Miller补偿导致的右平面零点问题,使得稳压器可以在宽负载电流范围下稳定工作。电路采用0.18μm BCD工艺进行设计,仿真结果表明,所设计的LDO电路静态电流为56.3μA,在空载情况下的相位裕度为52°,3 A满载时相位裕度达到85°,在全负载范围内均具有良好的稳定性。
