The boundary scan architecture and its basic principle of board level built in test(BIT) technology are presented. A design for board level built in test and the method to implement test tool are brought forward.
随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相...随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相应测试方法研究。提出了一种高效的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法。该方法以ZYNQ MPSOC为核心,设计了一种直达应用层面的系统级测试装置,从而减少了与物理层直接交互的行为,有效降低了测试装置及程序开发难度。经试验验证,提出的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法能够用于以太网PHY芯片测试。展开更多
文摘The boundary scan architecture and its basic principle of board level built in test(BIT) technology are presented. A design for board level built in test and the method to implement test tool are brought forward.
