Microprocessor development emphasizes hardware and software co design. Hw/Sw co design is a modern technique aimed at shortening the time to market in designing the real time and embedded systems. Key feature of this ...Microprocessor development emphasizes hardware and software co design. Hw/Sw co design is a modern technique aimed at shortening the time to market in designing the real time and embedded systems. Key feature of this approach is simultaneous development of the program tools and the target processor to match software application. An effective co design flow must therefore support automatic software toolkits generation, without loss of optimizing efficiency. This has resulted in a paradigm shift towards a language based design methodology for microprocessor optimization and exploration. This paper proposes a formal grammar, UNI SPEC, which supports the automatic generation of assemblers, to describe the translation rules from assembly to binary. Based on UNI SPEC, it implements two typical applications, i.e., automatically generating the assembler and the test suites.展开更多
This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the ...This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the difficulty of asynchronous design and performance analysis, both complete asynchronous and partial asynchronous structures aere designed and compared. Results of comparison with the well-Rnown industrial product ARM922T verify that about 30% and 40% performance improvement of the partiM and complete asynchronous complex pipelines can be obtained respectively. The design methodologies can also be used in the design of other asynchronous pipelines.展开更多
The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in plac e of the complete instruction set during generatio...The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in plac e of the complete instruction set during generation of testing procedures is giv en in terms of the processor presentation matrix between micro-operators and in structions of MCDSP.展开更多
In order to gain the great performance of ASIP, this paper discusses different aspects of an ASIP instruction set specification like syntax, encoding, constraints as welt as behaviors, and introduces our ADL model bas...In order to gain the great performance of ASIP, this paper discusses different aspects of an ASIP instruction set specification like syntax, encoding, constraints as welt as behaviors, and introduces our ADL model based methodology to check them. The automatic generation of test cases based on our straight-forward instruction representation is shown, and the efficient generation of them with good coverage is shown as well. The verification of the constraint checker, a very important tool for programmer, is performed. Results show that the toolkit can find some errors in previous delivery tools, and the introduced methodology verifies the feasibility of our instruction set specification.展开更多
A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied...A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied component,DBTs can not only get rid of the dependence of machine(s),but also get better performance.From our systematical study and evaluation,experimental results demonstrate that if V-IIS is well designed,without affecting the other optimizing measures,this could make DBT's performance close to those who do not have intermediate instructions.This study is an important step towards the grand goal of high performance "multi-source" and "multi-target" dynamic binary translation.展开更多
The cost of the central register file and the size of the program code limit the scalability of very long instruction word（VLIW） processors with increasing numbers of functional units.This paper presents the archite...The cost of the central register file and the size of the program code limit the scalability of very long instruction word（VLIW） processors with increasing numbers of functional units.This paper presents the architectural design of a six-way VLIW digital signal processor（DSP） with clustered register files.The architecture uses a variable length instruction set and supports dynamic instruction dispatching.The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM.A compiler based on the Open64 was developed for the system.Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.展开更多
超高温熔盐泵测试装置是一套用于研究泵、阀、换热器等关键设备在高温熔盐工况下性能的装置。为增强其控制系统的国产化程度及核心控制器的自主可控性,在国产自主指令架构LoongArch上设计研发了基于实验物理与工业控制系统(Experimental...超高温熔盐泵测试装置是一套用于研究泵、阀、换热器等关键设备在高温熔盐工况下性能的装置。为增强其控制系统的国产化程度及核心控制器的自主可控性,在国产自主指令架构LoongArch上设计研发了基于实验物理与工业控制系统(Experimental Physics and Industrial Control System,EPICS)的实时控制器。首先将EPICS、IgH EtherCAT Master等软件移植到基于LoongArch的嵌入式开发板上,解决软件与指令架构不适配的问题,实现控制程序的编写与执行、EtherCAT主从站通讯等功能,并对控制器的最小总线扫描周期进行测试;然后,针对超高温熔盐泵测试装置的控制需求,利用自主研发的EPICS扩展插件在该控制器上实现了PID温度控制、气路流量监测等功能;最后,在实际工况下对控制器的实时性、CPU使用率等指标进行测试分析,评估控制器的性能表现。实验数据表明:该控制器的最小总线扫描周期为50 ms,控制任务执行的延迟时间最大为12.85 ms,CPU性能表现良好,满足该项目的应用需求。该控制器已成功融入超高温熔盐泵测试装置的控制系统,取代了原x86服务器,目前在稳定运行中。展开更多
Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, wi...Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi- core ISS （MCISS） is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ＂save and restore＂ mechanism, the verification procedure and the debugging are speeding up greatly.展开更多
文摘Microprocessor development emphasizes hardware and software co design. Hw/Sw co design is a modern technique aimed at shortening the time to market in designing the real time and embedded systems. Key feature of this approach is simultaneous development of the program tools and the target processor to match software application. An effective co design flow must therefore support automatic software toolkits generation, without loss of optimizing efficiency. This has resulted in a paradigm shift towards a language based design methodology for microprocessor optimization and exploration. This paper proposes a formal grammar, UNI SPEC, which supports the automatic generation of assemblers, to describe the translation rules from assembly to binary. Based on UNI SPEC, it implements two typical applications, i.e., automatically generating the assembler and the test suites.
基金the Research Project of China Military Department (No. 6130325)
文摘This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the difficulty of asynchronous design and performance analysis, both complete asynchronous and partial asynchronous structures aere designed and compared. Results of comparison with the well-Rnown industrial product ARM922T verify that about 30% and 40% performance improvement of the partiM and complete asynchronous complex pipelines can be obtained respectively. The design methodologies can also be used in the design of other asynchronous pipelines.
文摘The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in plac e of the complete instruction set during generation of testing procedures is giv en in terms of the processor presentation matrix between micro-operators and in structions of MCDSP.
文摘In order to gain the great performance of ASIP, this paper discusses different aspects of an ASIP instruction set specification like syntax, encoding, constraints as welt as behaviors, and introduces our ADL model based methodology to check them. The automatic generation of test cases based on our straight-forward instruction representation is shown, and the efficient generation of them with good coverage is shown as well. The verification of the constraint checker, a very important tool for programmer, is performed. Results show that the toolkit can find some errors in previous delivery tools, and the introduced methodology verifies the feasibility of our instruction set specification.
基金Projects(12R21414600)supported by Shanghai Municipal Science and Technology Commission,China
文摘A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied component,DBTs can not only get rid of the dependence of machine(s),but also get better performance.From our systematical study and evaluation,experimental results demonstrate that if V-IIS is well designed,without affecting the other optimizing measures,this could make DBT's performance close to those who do not have intermediate instructions.This study is an important step towards the grand goal of high performance "multi-source" and "multi-target" dynamic binary translation.
基金Supported by the National Natural Science Foundation of China (No.60236020)the Specialized Research Fund for the Doctoral Program of Higher Education of MOE,China (No.20050003083)
文摘The cost of the central register file and the size of the program code limit the scalability of very long instruction word（VLIW） processors with increasing numbers of functional units.This paper presents the architectural design of a six-way VLIW digital signal processor（DSP） with clustered register files.The architecture uses a variable length instruction set and supports dynamic instruction dispatching.The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM.A compiler based on the Open64 was developed for the system.Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.
文摘超高温熔盐泵测试装置是一套用于研究泵、阀、换热器等关键设备在高温熔盐工况下性能的装置。为增强其控制系统的国产化程度及核心控制器的自主可控性,在国产自主指令架构LoongArch上设计研发了基于实验物理与工业控制系统(Experimental Physics and Industrial Control System,EPICS)的实时控制器。首先将EPICS、IgH EtherCAT Master等软件移植到基于LoongArch的嵌入式开发板上,解决软件与指令架构不适配的问题,实现控制程序的编写与执行、EtherCAT主从站通讯等功能,并对控制器的最小总线扫描周期进行测试;然后,针对超高温熔盐泵测试装置的控制需求,利用自主研发的EPICS扩展插件在该控制器上实现了PID温度控制、气路流量监测等功能;最后,在实际工况下对控制器的实时性、CPU使用率等指标进行测试分析,评估控制器的性能表现。实验数据表明:该控制器的最小总线扫描周期为50 ms,控制任务执行的延迟时间最大为12.85 ms,CPU性能表现良好,满足该项目的应用需求。该控制器已成功融入超高温熔盐泵测试装置的控制系统,取代了原x86服务器,目前在稳定运行中。
文摘Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi- core ISS （MCISS） is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ＂save and restore＂ mechanism, the verification procedure and the debugging are speeding up greatly.
