摘要
RISC-V架构凭借其开放性和模块化的指令集架构(ISA)设计,为特定应用及其软件生态系统的定制指令集成提供了良好支持,使其能够高效处理复杂算法并执行重复性操作。然而,由于操作数数量的限制,为RISC-V处理器设计加速指令仍面临挑战。传统处理器加速方法通常采用“2输入1输出”模型,这在一定程度上限制了复杂操作的灵活性与执行效率。为突破该限制,提出了一种多操作数增强指令集的设计方法。该方法通过引入多操作数加速机制,突破了传统模型的结构性约束,为多输入多输出任务提供了灵活的指令接口。为验证所提机制的有效性,基于Western Digital开源的RISC-V VeeR EH1处理器核实现了该设计,并在FPGA平台上进行了基准测试,涵盖SHA-256,SHA-1以及FIR/IIR滤波器等典型算法。实验结果表明,在FPGA平台上的逻辑资源开销控制在3%以内的情况下,处理器性能最高提升可达14%。与传统“2输入1输出”加速方法相比,所提出的增强指令集设计能够显著提升RISC-V在复杂任务处理中的性能,展示了其在嵌入式计算和专用加速领域的潜在优势。
The RISC-V architecture,with its open and modular instruction set architecture(ISA)design,facilitates the integration of customized instructions tailored to specific applications and their software ecosystems,enabling efficient processing of complex algorithms and repetitive operations.However,designing acceleration instructions for RISC-V processors presents significant challenges,primarily due to limitations in operand quantity.Traditional acceleration methods typically adopt a 2-input-1-output model,which restricts the flexibility and efficiency of complex operations.To address these limitations,this method proposes a multi-operand acceleration mechanism that breaks the conventional 2-input-1-output constraint by providing a flexible interface for multiple inputs and outputs.The mechanism is validated through benchmark tests on an FPGA platform,including SHA-256,SHA-1,and FIR/IIR filter algorithms,conducted on Western Digital’s open-source RISC-V VeeR EH1 core.Experimental results demonstrate a performance improvement of up to 14%while maintaining hardware overhead at or below 3%.Compared to traditional 2-input-1-output acceleration methods,the proposed enhanced instruction set design significantly enhances the processing efficiency of RISC-V cores,demonstrating its superior capability in embedded computing and domain-specific acceleration applications.
作者
张钰儿
席宇浩
刘鹏
ZHANG Yu'er;XI Yuhao;LIU Peng(College of Information Science&Electronic Engineering,Zhejiang University,Hangzhou 310027,China)
出处
《计算机工程与科学》
北大核心
2025年第6期968-975,共8页
Computer Engineering & Science
关键词
RISC-V
自定义指令
软硬件协同设计
reduced instruction set computer-V(RISC-V)
custom instructions
hardware-software co-design
