Simulations of photoresist etching,aerial image,exposure,and post-bake processes are integrated to obtain a photolithography process simulation for microelectromechanical system（MEMS） and integrated circuit（IC） fa...Simulations of photoresist etching,aerial image,exposure,and post-bake processes are integrated to obtain a photolithography process simulation for microelectromechanical system（MEMS） and integrated circuit（IC） fabrication based on three-dimensional （3D） cellular automata（CA）. The simulation results agree well with available experimental results. This indicates that the 3D dynamic CA model for the photoresist etching simulation and the 3D CA model for the post-bake simulation could be useful for the monolithic simulation of various lithography processes. This is determined to be useful for the device-sized fabrication process simulation of IC and MEMS.展开更多
Dynamic infrared scene simulation is for discovering and solving the problems encountered in designing, developing and manufacturing infrared imaging guidance weapons. The infrared scene simulation is explored by usin...Dynamic infrared scene simulation is for discovering and solving the problems encountered in designing, developing and manufacturing infrared imaging guidance weapons. The infrared scene simulation is explored by using the digital grayscale modulation method. The infrared image modulation model of a digital micro-mirror device （DMD） is established and then the infrared scene simulator prototype which is based on DMD grayscale modulation is developed. To evaluate its main parameters such as resolution, contrast, minimum temperature difference, gray scale, various DMD subsystems such as signal decoding, image normalization, synchronization drive, pulse width modulation （PWM） and DMD chips are designed. The infrared scene simulator is tested on a certain infrared missile seeker. The test results show preliminarily that the infrared scene simulator has high gray scale, small geometrical distortion and highly resolvable imaging resolution and contrast and yields high-fidelity images, thus being able to meet the requirements for the infrared scene simulation inside a laboratory.展开更多
Large eddy simulation （LES） using the Smagorinsky eddy viscosity model is added to the two-dimensional nine velocity components （D2Q9） lattice Boltzmann equation （LBE） with multi-relaxation-time （MRT） to simul...Large eddy simulation （LES） using the Smagorinsky eddy viscosity model is added to the two-dimensional nine velocity components （D2Q9） lattice Boltzmann equation （LBE） with multi-relaxation-time （MRT） to simulate incompressible turbulent cavity flows with the Reynolds numbers up to 1 × 10^7. To improve the computation efficiency of LBM on the numerical simulations of turbulent flows, the massively parallel computing power from a graphic processing unit （GPU） with a computing unified device architecture （CUDA） is introduced into the MRT-LBE-LES model. The model performs well, compared with the results from others, with an increase of 76 times in computation efficiency. It appears that the higher the Reynolds numbers is, the smaller the Smagorinsky constant should be, if the lattice number is fixed. Also, for a selected high Reynolds number and a selected proper Smagorinsky constant, there is a minimum requirement for the lattice number so that the Smagorinsky eddy viscosity will not be excessively large.展开更多
A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all othe...A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability. According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate-all- around rectangular （GAAR） devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen- tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.展开更多
A microtubule gliding assay is a biological experiment observing the dynamics of microtubules driven by motor proteins fixed on a glass surface. When appropriate microtubule interactions are set up on gliding assay ex...A microtubule gliding assay is a biological experiment observing the dynamics of microtubules driven by motor proteins fixed on a glass surface. When appropriate microtubule interactions are set up on gliding assay experiments, microtubules often organize and create higher-level dynamics such as ring and bundle structures. In order to reproduce such higher-level dynamics on computers, we have been focusing on making a real-time 3D microtubule simulation. This real-time 3D microtubule simulation enables us to gain more knowledge on microtubule dynamics and their swarm movements by means of adjusting simulation paranleters in a real-time fashion. One of the technical challenges when creating a real-time 3D simulation is balancing the 3D rendering and the computing performance. Graphics processor unit （GPU） programming plays an essential role in balancing the millions of tasks, and makes this real-time 3D simulation possible. By the use of general-purpose computing on graphics processing units （GPGPU） programming we are able to run the simulation in a massively parallel fashion, even when dealing with more complex interactions between microtubules such as overriding and snuggling. Due to performance being an important factor, a performance n, odel has also been constructed from the analysis of the microtubule simulation and it is consistent with the performance measurements on different GPGPU architectures with regards to the number of cores and clock cycles.展开更多
The enhancement of mobility has always been a research focus in the field of thin-film transistors(TFTs).In this paper,we report a method using ultra-thin HfO2to improve the electrical performance of indium gallium zi...The enhancement of mobility has always been a research focus in the field of thin-film transistors(TFTs).In this paper,we report a method using ultra-thin HfO2to improve the electrical performance of indium gallium zinc oxide(IGZO)TFTs.HfO2not only repairs the surface morphology of the active layer,but also increases the carrier concentration.When the thickness of the HfO_(2) film was 3 nm,the mobility of the device was doubled(14.9 cm^(2)·V^(-1)·s^(-1)→29.6 cm^(2)·V^(-1)·s^(-1)),and the device exhibited excellent logic device performance.This paper provides a simple and effective method to enhance the electrical performance of IGZO TFTs,offering new ideas and experimental foundation for research into high-performance metal oxide(MO)TFTs.展开更多
We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinit...We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.展开更多
Hot tearing is one of the most serious defects during the casting solidification process.In this study,a new type of multichannel"cross"hot tearing device was designed.The hot cracks initiation and propagati...Hot tearing is one of the most serious defects during the casting solidification process.In this study,a new type of multichannel"cross"hot tearing device was designed.The hot cracks initiation and propagation were predicted by the relationship between temperature,shrinkage force and solidification time during the casting solidification process.The reliability and practicability of the multichannel"cross"hot tearing device were verified by casting experiments and numerical simulations.The theoretical calculation based on Clyne-Davies model and numerical simulation results show that the hot tearing tendency decreases in the order:2024 Al alloy>Al-Cu alloy>Al-Si alloy at a pouring temperature of 670°C and a mold temperature of 25°C.Feeding of liquid films at the end of solidification plays an important role in the propagation process of hot tearing.The decrease of hot tearing tendency is attributed to the feeding of liquid film and intergranular bridging.展开更多
With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have eme...With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.展开更多
随着宇航工程的发展,以第三代半导体SiC为代表的新型元器件将极大提高宇航器性能,将成为未来空间应用的主力军。新型元器件的空间应用要应对空间辐射效应带来的风险,需要开展实验分析和相关保障研究。对1200 V SiC器件进行了单粒子仿真...随着宇航工程的发展,以第三代半导体SiC为代表的新型元器件将极大提高宇航器性能,将成为未来空间应用的主力军。新型元器件的空间应用要应对空间辐射效应带来的风险,需要开展实验分析和相关保障研究。对1200 V SiC器件进行了单粒子仿真和重离子环境实验,创新性地提出了SiC器件在单粒子环境下的失效机理,分析了导致SiC器件失效的原因,给出了仿真条件下SiC器件不同区域的单粒子敏感度。展开更多
文摘Simulations of photoresist etching,aerial image,exposure,and post-bake processes are integrated to obtain a photolithography process simulation for microelectromechanical system（MEMS） and integrated circuit（IC） fabrication based on three-dimensional （3D） cellular automata（CA）. The simulation results agree well with available experimental results. This indicates that the 3D dynamic CA model for the photoresist etching simulation and the 3D CA model for the post-bake simulation could be useful for the monolithic simulation of various lithography processes. This is determined to be useful for the device-sized fabrication process simulation of IC and MEMS.
基金co-supported by China Postdoctoral Science Foundation (20090461314)
文摘Dynamic infrared scene simulation is for discovering and solving the problems encountered in designing, developing and manufacturing infrared imaging guidance weapons. The infrared scene simulation is explored by using the digital grayscale modulation method. The infrared image modulation model of a digital micro-mirror device （DMD） is established and then the infrared scene simulator prototype which is based on DMD grayscale modulation is developed. To evaluate its main parameters such as resolution, contrast, minimum temperature difference, gray scale, various DMD subsystems such as signal decoding, image normalization, synchronization drive, pulse width modulation （PWM） and DMD chips are designed. The infrared scene simulator is tested on a certain infrared missile seeker. The test results show preliminarily that the infrared scene simulator has high gray scale, small geometrical distortion and highly resolvable imaging resolution and contrast and yields high-fidelity images, thus being able to meet the requirements for the infrared scene simulation inside a laboratory.
基金supported by College of William and Mary,Virginia Institute of Marine Science for the study environment
文摘Large eddy simulation （LES） using the Smagorinsky eddy viscosity model is added to the two-dimensional nine velocity components （D2Q9） lattice Boltzmann equation （LBE） with multi-relaxation-time （MRT） to simulate incompressible turbulent cavity flows with the Reynolds numbers up to 1 × 10^7. To improve the computation efficiency of LBM on the numerical simulations of turbulent flows, the massively parallel computing power from a graphic processing unit （GPU） with a computing unified device architecture （CUDA） is introduced into the MRT-LBE-LES model. The model performs well, compared with the results from others, with an increase of 76 times in computation efficiency. It appears that the higher the Reynolds numbers is, the smaller the Smagorinsky constant should be, if the lattice number is fixed. Also, for a selected high Reynolds number and a selected proper Smagorinsky constant, there is a minimum requirement for the lattice number so that the Smagorinsky eddy viscosity will not be excessively large.
文摘A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability. According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate-all- around rectangular （GAAR） devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen- tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.
基金supported by a Grant-in-Aid for Scientific Research on Innovation Areas "Molecular Robotics"(No.24104004) of the Ministry of Education,Culture,Sports,Science,and Technology,Japan
文摘A microtubule gliding assay is a biological experiment observing the dynamics of microtubules driven by motor proteins fixed on a glass surface. When appropriate microtubule interactions are set up on gliding assay experiments, microtubules often organize and create higher-level dynamics such as ring and bundle structures. In order to reproduce such higher-level dynamics on computers, we have been focusing on making a real-time 3D microtubule simulation. This real-time 3D microtubule simulation enables us to gain more knowledge on microtubule dynamics and their swarm movements by means of adjusting simulation paranleters in a real-time fashion. One of the technical challenges when creating a real-time 3D simulation is balancing the 3D rendering and the computing performance. Graphics processor unit （GPU） programming plays an essential role in balancing the millions of tasks, and makes this real-time 3D simulation possible. By the use of general-purpose computing on graphics processing units （GPGPU） programming we are able to run the simulation in a massively parallel fashion, even when dealing with more complex interactions between microtubules such as overriding and snuggling. Due to performance being an important factor, a performance n, odel has also been constructed from the analysis of the microtubule simulation and it is consistent with the performance measurements on different GPGPU architectures with regards to the number of cores and clock cycles.
基金Project supported by the National Natural Science Foundation of China(Grant No.62441407)the Natural Science Basic Research Program of Shaanxi(Grant No.2024JCYBQN-0631)+1 种基金the Natural Science Foundation of Shaanxi Provincial Department of Education(Grant No.23JK0482)the Shaanxi Province Key R&D Program General Project-Industrial Field(Grant No.2024GX-YBXM-085)。
文摘The enhancement of mobility has always been a research focus in the field of thin-film transistors(TFTs).In this paper,we report a method using ultra-thin HfO2to improve the electrical performance of indium gallium zinc oxide(IGZO)TFTs.HfO2not only repairs the surface morphology of the active layer,but also increases the carrier concentration.When the thickness of the HfO_(2) film was 3 nm,the mobility of the device was doubled(14.9 cm^(2)·V^(-1)·s^(-1)→29.6 cm^(2)·V^(-1)·s^(-1)),and the device exhibited excellent logic device performance.This paper provides a simple and effective method to enhance the electrical performance of IGZO TFTs,offering new ideas and experimental foundation for research into high-performance metal oxide(MO)TFTs.
文摘We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.
基金This work was financially supported by the National Natural Science Foundation of China(Grant No.51875365).
文摘Hot tearing is one of the most serious defects during the casting solidification process.In this study,a new type of multichannel"cross"hot tearing device was designed.The hot cracks initiation and propagation were predicted by the relationship between temperature,shrinkage force and solidification time during the casting solidification process.The reliability and practicability of the multichannel"cross"hot tearing device were verified by casting experiments and numerical simulations.The theoretical calculation based on Clyne-Davies model and numerical simulation results show that the hot tearing tendency decreases in the order:2024 Al alloy>Al-Cu alloy>Al-Si alloy at a pouring temperature of 670°C and a mold temperature of 25°C.Feeding of liquid films at the end of solidification plays an important role in the propagation process of hot tearing.The decrease of hot tearing tendency is attributed to the feeding of liquid film and intergranular bridging.
基金The authors would like to thank the management team and all our team members in Shanghai ICRD center.
文摘With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.
文摘随着宇航工程的发展,以第三代半导体SiC为代表的新型元器件将极大提高宇航器性能,将成为未来空间应用的主力军。新型元器件的空间应用要应对空间辐射效应带来的风险,需要开展实验分析和相关保障研究。对1200 V SiC器件进行了单粒子仿真和重离子环境实验,创新性地提出了SiC器件在单粒子环境下的失效机理,分析了导致SiC器件失效的原因,给出了仿真条件下SiC器件不同区域的单粒子敏感度。
