In this paper,a fifth-order fully differential interface circuit( IC) is presented to improve the noise performance for micromechanical sigma-delta( Σ-Δ) accelerometer. A lead compensator is adopted to ensure the st...In this paper,a fifth-order fully differential interface circuit( IC) is presented to improve the noise performance for micromechanical sigma-delta( Σ-Δ) accelerometer. A lead compensator is adopted to ensure the stability of the closed-loop high-order system. A low noise capacitance detection circuit is described with a correlated-double-sampling( CDS) technique to decrease 1 /f noise and offset of the operational amplifier. This paper also proposes a self-test technique for the interface circuit to test the harmonic distortion. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in larger dynamic range( DR). The layout of the IC is implemented in a standard 0. 6 μm CMOS technology and operates at a sampling frequency of 250 kHz. The interface consumes 20 mW from a 5 V supply. The post-simulation results indicate that the noise floor of the digital accelerometer is about- 140 dBV /Hz1 /2at low frequency. The sensitivity is 2. 5 V /g and the nonlinearity is 0. 11%. The self-test function is achieved with 98. 2 dB thirdorder harmonic distortion detection based on the electrostatic force feedback linearization.展开更多
基金Sponsored by the National Natural Science Foundation of China(Grant No.61204121)the National Hi-Tech Research and Development Program of China(Grant No.2013AA041107)
文摘In this paper,a fifth-order fully differential interface circuit( IC) is presented to improve the noise performance for micromechanical sigma-delta( Σ-Δ) accelerometer. A lead compensator is adopted to ensure the stability of the closed-loop high-order system. A low noise capacitance detection circuit is described with a correlated-double-sampling( CDS) technique to decrease 1 /f noise and offset of the operational amplifier. This paper also proposes a self-test technique for the interface circuit to test the harmonic distortion. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in larger dynamic range( DR). The layout of the IC is implemented in a standard 0. 6 μm CMOS technology and operates at a sampling frequency of 250 kHz. The interface consumes 20 mW from a 5 V supply. The post-simulation results indicate that the noise floor of the digital accelerometer is about- 140 dBV /Hz1 /2at low frequency. The sensitivity is 2. 5 V /g and the nonlinearity is 0. 11%. The self-test function is achieved with 98. 2 dB thirdorder harmonic distortion detection based on the electrostatic force feedback linearization.
