期刊文献+

内建自测试多特征混淆模型

Aliasing probability model with multiple characteristics in BIST
在线阅读 下载PDF
导出
摘要 特征分析广泛应用于内建自测试体系的响应分析中,通过建立多输入线性移位寄存器的2状态马尔可夫模型和4状态马尔可夫模型,研究了时间无关空间相关及时空均相关下的响应分析器测试序列长度与混淆概率关系,获得混淆的精确数学模型。通过对某控制系统单多特征内建自测试体系混淆结果比较表明:多特征分析可获得更小的混淆概率和更高的测试效率。 Characteristic analysis is widely used in the process of response analysis for the architecture of BIST.Models of 2-state Markov process and 4-state Markov process were established for the multiple input signature register(MISR),which was used for studying the relations between the test length and aliasing error probability for the response analysis under the conditions of the time-independence space-dependence model and time space-dependence model.The accurate expression of aliasing error probability was derived.According to the result of aliasing probability for some control system,the method of multiple characteristics analysis for BIST was presented to achieve the lower aliasing error probability and higher test efficiency.
出处 《海军工程大学学报》 CAS 北大核心 2010年第2期74-78,共5页 Journal of Naval University of Engineering
关键词 内建自测试 线性反馈移位寄存器 混淆概率 马尔可夫过程 built-in self test linear feedback shift register aliasing probability Markov process
  • 相关文献

参考文献5

  • 1ZHAO Jian-wu,SHI Yi-bing,LI Yan-jun.Aliasing probability for single input linear feedback signature regis-ters[C]// The Eighth International Conference on Electronic Measurement and Instruments.Xi'an:Journal of Electronic Measurement and Instrument,2007.
  • 2ELSAHOLY M S.Exact analytical model for the AEP of control signals[J].IEEE Proc-Circuits Devices Syst.,2002,149(4):212-216.
  • 3DAS S R.Getting errors to catch themselves self-testing of VLSI circuits with built-in hardware[J].IEEE Trans.Instrum.Meas.,2005,54(3):941-954.
  • 4BISWAS S,RAS S R,PETRIU E M.Space compactor design in VLSI circuits based on graph theoretic con-cepts[J].IEEE Trans.Instrum.Meas.,2006,55(4):1106-1118.
  • 5谢永乐,王玉文,陈光.数字IP芯核的多特征比较内建自测试方法(英文)[J].四川大学学报(工程科学版),2006,38(6):153-158. 被引量:2

二级参考文献6

  • 1Abdula M F,Ravikumar C P,Kumar A.Built-In-Self-Test based on multiple on-chip signature checking[J].Journal of Electronic Testing:Theory and Application (JETTA),1999,14:227-244.
  • 2Karimi F,Navabi Z,Meleis W M,et al.Using data compression in automatic test equipment for system-on-chip testing[J].IEEE Transactions on Instrumentation and Measurement,2004,53(2):308-317.
  • 3Pradhan D K,Gupta S K,Karpovsky M G.Aliasing probability for multiple input signature analyzer[J].IEEE Transaction on Computers,1990,39(4):586-591.
  • 4Edirisooriya G,Edirisooriya S,Robinson J P.Time and space correlated error in signature analysis[C].IEEE 11th International Conference on VLSI Test Symposium,Califonia,USA,1993:275-281.
  • 5Pullman N J.Matrix theory and it's application:selected topics[M].New York and Basel:Marcel Dekker Inc,1976.
  • 6Touba N A,McCluskey E J.Bit-fixing in pseudorandom sequences for scan BIST[J].IEEE Transaction on Computer-Aided Design,2001,20(4):545-555.

共引文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部