A single chip Synchronous Digital Hierarchy STM N processor has been developed. The cell based chip has been fabricated in a 0.5μm CMOS process. It contains 280k gates and 240pins. The chip can be configured in sev...A single chip Synchronous Digital Hierarchy STM N processor has been developed. The cell based chip has been fabricated in a 0.5μm CMOS process. It contains 280k gates and 240pins. The chip can be configured in several operation modes: STM N overhead terminator, E4(139.264Mb/s) mapper, ADM(Add/Drop Multiplex) E1(2.048Mb/s) mapper, 150Mb/s ATM interface and 2Mb/s ATM interface. This paper describes the architecture of the IC, and the chips several interesting features.展开更多
文摘A single chip Synchronous Digital Hierarchy STM N processor has been developed. The cell based chip has been fabricated in a 0.5μm CMOS process. It contains 280k gates and 240pins. The chip can be configured in several operation modes: STM N overhead terminator, E4(139.264Mb/s) mapper, ADM(Add/Drop Multiplex) E1(2.048Mb/s) mapper, 150Mb/s ATM interface and 2Mb/s ATM interface. This paper describes the architecture of the IC, and the chips several interesting features.
