摘要
首先在明确40Gbit/sSDH(STM 256)光纤通信设备要求的基础上,确定了芯片与外围电路的电路、功能和时序接口,制订了满足设备需要并利于ASIC实现的芯片技术规范;其次,进行了芯片的总体方案设计,按照自顶向下的全正向设计方法进行了芯片的逻辑结构设计,并合理安排了芯片的寄存器结构;行为级仿真结果表明,方案是可行的.
This thesis focuses on the toplevel design of the digital cross connect (DXC) chip. Based on the precept of 40 Gbit/s SDH (STM-256) fiber-optical communication devices & system, the design target of the chip is specified at the beginning, the functions, circuit and timing interface are clearly defined. Then the logic architecture is discussed with top to down design method. At last, the arrangements of registers are given.
出处
《光通信研究》
北大核心
2004年第3期45-48,共4页
Study on Optical Communications
基金
国家"十五"科技攻关计划资助项目(2002BA106B06)
国家"八六三计划"资助项目(2003AA1Z1190)
