This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approx- imation register （SAR） analog-to-digital converter （ADC） for multi-channel CdZnTe （CZT） detector applicatio...This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approx- imation register （SAR） analog-to-digital converter （ADC） for multi-channel CdZnTe （CZT） detector applications. In order to improve the SAR-ADC＇s accuracy, a novel comparator is proposed in which the offset voltage is self- calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio （SINAD） of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 ×1080μm2.展开更多
SAR ADC(Successive Approximation Register Analog Digital Converter)是一种低功耗、结构简单、性能可靠的ADC,其精度和采样速率的可选范围较大,因此被广泛应用于各种集成电路中。传统SAR ADC采用电容阵列提供模拟参考电压,但电容阵...SAR ADC(Successive Approximation Register Analog Digital Converter)是一种低功耗、结构简单、性能可靠的ADC,其精度和采样速率的可选范围较大,因此被广泛应用于各种集成电路中。传统SAR ADC采用电容阵列提供模拟参考电压,但电容阵列需要较大面积,因此降低了单位晶圆的产出率,增加了成本。文中采用一种已有R2R DAC(Digital Analog Converter)结构代替电容阵列提供模拟参考电压以减小电路面积。相比传统电阻DAC结构,R2R DAC结构功耗更小。在电路设计中增加翻转电路消除共模噪声,在版图绘制时加入保护环和赝管来确保匹配度与可靠性。在精度相同的情况下,SAR ADC电路有效面积减小了约35%。抽取寄生参数后仿真所得ADC的ENOB(Effective Number of Bits)为9.93 bit,SNDR(Signal-to-Noise-and-Distortion Ratio)为61.51 dB,且在不同PVT(Process Voltage Temperature)情况下仿真的误差均小于1 LSB(Least Significant Number)。展开更多
基金supported by the Special-Funded Program on National Key Scientific Instruments and Equipment Development(No.2011YQ040082)
文摘This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approx- imation register （SAR） analog-to-digital converter （ADC） for multi-channel CdZnTe （CZT） detector applications. In order to improve the SAR-ADC＇s accuracy, a novel comparator is proposed in which the offset voltage is self- calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio （SINAD） of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 ×1080μm2.
文摘SAR ADC(Successive Approximation Register Analog Digital Converter)是一种低功耗、结构简单、性能可靠的ADC,其精度和采样速率的可选范围较大,因此被广泛应用于各种集成电路中。传统SAR ADC采用电容阵列提供模拟参考电压,但电容阵列需要较大面积,因此降低了单位晶圆的产出率,增加了成本。文中采用一种已有R2R DAC(Digital Analog Converter)结构代替电容阵列提供模拟参考电压以减小电路面积。相比传统电阻DAC结构,R2R DAC结构功耗更小。在电路设计中增加翻转电路消除共模噪声,在版图绘制时加入保护环和赝管来确保匹配度与可靠性。在精度相同的情况下,SAR ADC电路有效面积减小了约35%。抽取寄生参数后仿真所得ADC的ENOB(Effective Number of Bits)为9.93 bit,SNDR(Signal-to-Noise-and-Distortion Ratio)为61.51 dB,且在不同PVT(Process Voltage Temperature)情况下仿真的误差均小于1 LSB(Least Significant Number)。
