Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MO...Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.展开更多
A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide l...A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.展开更多
The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to ...The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.展开更多
The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche fa...The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.展开更多
Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade...Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOS- FETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator （DSPSOI） layers. Results show that the safety operation area （SOA） of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV-cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.展开更多
The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigat...The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.展开更多
A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and so...A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region.At OFF state,the low-k dielectric trench（LDT） can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time,the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally,ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics,such as low gateto -drain charge density（〈 0.6 nC/mm^2） and a robust safe operating area（0-84 V）.展开更多
It was demonstrated that heavy ions can induce large current-voltage （I-V） characteristics shift in commercial trench power MOSFETs, named single event microdose effect （SE-microdose effect）. A model is pre- sente...It was demonstrated that heavy ions can induce large current-voltage （I-V） characteristics shift in commercial trench power MOSFETs, named single event microdose effect （SE-microdose effect）. A model is pre- sented to describe this effect. This model calculates the charge deposition by a single heavy ion hitting oxide and the subsequent charge transport under an electric field. Holes deposited at the SiO2/Si interface by a Xe ion are calculated by using this model. The calculated results were then used in Sentaurus TCAD software to simulate a trench power MOSFET＇s I-V curve shift after a Xe ion has hit it. The simulation results are consistent with the related experiment＇s data. In the end, several factors which affect the SE-microdose effect in trench power MOSFETs are investigated by using this model.展开更多
We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of...We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.展开更多
Novel improved power metal oxide semiconductor field effect transistor （MOSFET） drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improv...Novel improved power metal oxide semiconductor field effect transistor （MOSFET） drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.展开更多
The paper investigates the zero temperature coefficient（ZTC） point of power MOSFET,based on the output characteristic of power MOSFET,the temperature coefficient of threshold voltage and the carrier mobility.It is f...The paper investigates the zero temperature coefficient（ZTC） point of power MOSFET,based on the output characteristic of power MOSFET,the temperature coefficient of threshold voltage and the carrier mobility.It is found that the gate voltage has a big effect on the ZTC point.The result indicates that there are three types of temperature coefficient under different gate voltage.When the gate voltage is near the threshold voltage,both the linear region and saturation region shows a large positive temperature coefficient.With the increase of gate voltage,the temperature coefficient of the linear region changes from positive to negative,when the saturation region still remains positive,giving rise to the ZTC point.When the gate voltage is high enough,the negative temperature coefficient is present on both the linear and saturation region,resulting in no ZTC point.According to the experimental result,the change of ZTC point as a function of temperature is larger when the gate voltage is higher.The carrier mobility is also discussed,displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.展开更多
Single event gate rupture（SEGR） is a very important failure mode for power MOSFETs when used in aerospace applications,and the cell regions are widely considered to be the most sensitive to SEGR.However, experimenta...Single event gate rupture（SEGR） is a very important failure mode for power MOSFETs when used in aerospace applications,and the cell regions are widely considered to be the most sensitive to SEGR.However, experimental results show that SEGR can also happen in the gate bus regions.In this paper,we used simulation tools to estimate three structures in power MOSFETs,and found that if certain conditions are met,areas other than cell regions can become sensitive to SEGR.Finally,some proposals are given as to how to reduce SEGR in different regions.展开更多
研究了重离子引起漏电退化损伤对1 200 V SiC MOSFET栅极可靠性的影响。结果表明,在Ta离子辐照下,V_(DS)在150 V至200 V时,器件漏电流由纳安增加至微安,通过微光显微镜(EMMI)发现损伤主要集中在器件的主结区。经过168 h的20 V栅压考核,...研究了重离子引起漏电退化损伤对1 200 V SiC MOSFET栅极可靠性的影响。结果表明,在Ta离子辐照下,V_(DS)在150 V至200 V时,器件漏电流由纳安增加至微安,通过微光显微镜(EMMI)发现损伤主要集中在器件的主结区。经过168 h的20 V栅压考核,漏电退化器件栅漏电由几微安升高至百微安,但最大跨导和转移特性均无明显变化。研究同时验证了在负栅压辐照条件下,器件栅极更易发生漏电。综上,本研究为SiC MOSFET辐照后栅极可靠性评估、抗辐照性能加固提出新的视角,对探讨天-地等效的重离子单粒子效应模拟实验方法具有一定参考意义。展开更多
基金supported by the National Natural Science Foundation of China under Grant No.11975305the West Light Foundation of The Chinese Academy of Sciences,Grant No.2017-XBQNXZ-B-008。
文摘Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.
基金Supported by the National Natural Science Foundation of China under Grant Nos 61404014 and 61405018the Fundamental Research Funds for the Central Universities under Grant Nos CDJZR12160003 and 106112014CDJZR168801
文摘A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.
基金Project supported by the National Natural Science Foundation of China(Grant No.12004329)Open Project of State Key Laboratory of Intense Pulsed Radiation Simulation and Effect(Grant No.SKLIPR2115)+1 种基金Postgraduate Research and Practice Innovation Program of Jiangsu Province(Grant No.SJCX22_1704)Innovative Science and Technology Platform Project of Cooperation between Yangzhou City and Yangzhou University,China(Grant Nos.YZ202026301 and YZ202026306)。
文摘The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.
文摘The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.
基金Project supported by the National Natural Science Foundation of China(No.61464002)the Grand Science and Technology Special Project in Guizhou Province of China(No.[2015]6006)the Ministry of Education Open Foundation for Semiconductor Power Device Reliability(No.010201)
文摘Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOS- FETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator （DSPSOI） layers. Results show that the safety operation area （SOA） of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV-cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.
文摘The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.
基金Project supported by the National Natural Science Foundation of China(Nos.60906037,60906038)the Fundamental Research Funds for the Central Universities,China(Nos.ZYGX2009J027,E022050205)the Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices
文摘A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region.At OFF state,the low-k dielectric trench（LDT） can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time,the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally,ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics,such as low gateto -drain charge density（〈 0.6 nC/mm^2） and a robust safe operating area（0-84 V）.
文摘It was demonstrated that heavy ions can induce large current-voltage （I-V） characteristics shift in commercial trench power MOSFETs, named single event microdose effect （SE-microdose effect）. A model is pre- sented to describe this effect. This model calculates the charge deposition by a single heavy ion hitting oxide and the subsequent charge transport under an electric field. Holes deposited at the SiO2/Si interface by a Xe ion are calculated by using this model. The calculated results were then used in Sentaurus TCAD software to simulate a trench power MOSFET＇s I-V curve shift after a Xe ion has hit it. The simulation results are consistent with the related experiment＇s data. In the end, several factors which affect the SE-microdose effect in trench power MOSFETs are investigated by using this model.
基金Project supported by the National Natural Science Foundation of China(Nos.61404161,61404068,61404169)
文摘We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.
基金supported by the National Natural Science Foundation of China(No.60876023).
文摘Novel improved power metal oxide semiconductor field effect transistor （MOSFET） drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.
文摘The paper investigates the zero temperature coefficient（ZTC） point of power MOSFET,based on the output characteristic of power MOSFET,the temperature coefficient of threshold voltage and the carrier mobility.It is found that the gate voltage has a big effect on the ZTC point.The result indicates that there are three types of temperature coefficient under different gate voltage.When the gate voltage is near the threshold voltage,both the linear region and saturation region shows a large positive temperature coefficient.With the increase of gate voltage,the temperature coefficient of the linear region changes from positive to negative,when the saturation region still remains positive,giving rise to the ZTC point.When the gate voltage is high enough,the negative temperature coefficient is present on both the linear and saturation region,resulting in no ZTC point.According to the experimental result,the change of ZTC point as a function of temperature is larger when the gate voltage is higher.The carrier mobility is also discussed,displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.
文摘Single event gate rupture（SEGR） is a very important failure mode for power MOSFETs when used in aerospace applications,and the cell regions are widely considered to be the most sensitive to SEGR.However, experimental results show that SEGR can also happen in the gate bus regions.In this paper,we used simulation tools to estimate three structures in power MOSFETs,and found that if certain conditions are met,areas other than cell regions can become sensitive to SEGR.Finally,some proposals are given as to how to reduce SEGR in different regions.
文摘研究了重离子引起漏电退化损伤对1 200 V SiC MOSFET栅极可靠性的影响。结果表明,在Ta离子辐照下,V_(DS)在150 V至200 V时,器件漏电流由纳安增加至微安,通过微光显微镜(EMMI)发现损伤主要集中在器件的主结区。经过168 h的20 V栅压考核,漏电退化器件栅漏电由几微安升高至百微安,但最大跨导和转移特性均无明显变化。研究同时验证了在负栅压辐照条件下,器件栅极更易发生漏电。综上,本研究为SiC MOSFET辐照后栅极可靠性评估、抗辐照性能加固提出新的视角,对探讨天-地等效的重离子单粒子效应模拟实验方法具有一定参考意义。
