Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MO...Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.展开更多
A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide l...A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.展开更多
The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to ...The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.展开更多
研究了重离子引起漏电退化损伤对1 200 V SiC MOSFET栅极可靠性的影响。结果表明,在Ta离子辐照下,V_(DS)在150 V至200 V时,器件漏电流由纳安增加至微安,通过微光显微镜(EMMI)发现损伤主要集中在器件的主结区。经过168 h的20 V栅压考核,...研究了重离子引起漏电退化损伤对1 200 V SiC MOSFET栅极可靠性的影响。结果表明,在Ta离子辐照下,V_(DS)在150 V至200 V时,器件漏电流由纳安增加至微安,通过微光显微镜(EMMI)发现损伤主要集中在器件的主结区。经过168 h的20 V栅压考核,漏电退化器件栅漏电由几微安升高至百微安,但最大跨导和转移特性均无明显变化。研究同时验证了在负栅压辐照条件下,器件栅极更易发生漏电。综上,本研究为SiC MOSFET辐照后栅极可靠性评估、抗辐照性能加固提出新的视角,对探讨天-地等效的重离子单粒子效应模拟实验方法具有一定参考意义。展开更多
The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche fa...The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.展开更多
Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade...Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOS- FETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator （DSPSOI） layers. Results show that the safety operation area （SOA） of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV-cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.展开更多
The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigat...The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.展开更多
A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and so...A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region.At OFF state,the low-k dielectric trench（LDT） can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time,the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally,ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics,such as low gateto -drain charge density（〈 0.6 nC/mm^2） and a robust safe operating area（0-84 V）.展开更多
基金supported by the National Natural Science Foundation of China under Grant No.11975305the West Light Foundation of The Chinese Academy of Sciences,Grant No.2017-XBQNXZ-B-008。
文摘Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.
基金Supported by the National Natural Science Foundation of China under Grant Nos 61404014 and 61405018the Fundamental Research Funds for the Central Universities under Grant Nos CDJZR12160003 and 106112014CDJZR168801
文摘A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.
基金Project supported by the National Natural Science Foundation of China(Grant No.12004329)Open Project of State Key Laboratory of Intense Pulsed Radiation Simulation and Effect(Grant No.SKLIPR2115)+1 种基金Postgraduate Research and Practice Innovation Program of Jiangsu Province(Grant No.SJCX22_1704)Innovative Science and Technology Platform Project of Cooperation between Yangzhou City and Yangzhou University,China(Grant Nos.YZ202026301 and YZ202026306)。
文摘The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.
文摘研究了重离子引起漏电退化损伤对1 200 V SiC MOSFET栅极可靠性的影响。结果表明,在Ta离子辐照下,V_(DS)在150 V至200 V时,器件漏电流由纳安增加至微安,通过微光显微镜(EMMI)发现损伤主要集中在器件的主结区。经过168 h的20 V栅压考核,漏电退化器件栅漏电由几微安升高至百微安,但最大跨导和转移特性均无明显变化。研究同时验证了在负栅压辐照条件下,器件栅极更易发生漏电。综上,本研究为SiC MOSFET辐照后栅极可靠性评估、抗辐照性能加固提出新的视角,对探讨天-地等效的重离子单粒子效应模拟实验方法具有一定参考意义。
文摘碳化硅(SiC)MOSFET器件的短路耐受能力差是阻碍其广泛应用的关键难题,对于国产高压SiC MOSFET器件,其短路保护研发缺乏有力的技术、经验支撑。同时,缺乏快速、准确的仿真模型也是国产高压SiC MOSFET器件应用研发面临的核心问题之一。为此,该文提出一种适用于高压SiC MOSFET器件的、考虑器件实际物理特性的、可准确描述器件短路故障中电流、电压等外特性的行为模型。该行为模型针对高压SiC MOSFET的特点修正沟道电流模型中的电压,并基于元胞层面的电流路径对JFET区及漂移区电阻进行建模。该模型考虑了国产高压SiC MOSFET的实际器件设计、工艺等因素的影响,依据半导体、器件物理计算模型的关键参数,提升模型在短路故障仿真中的精度。并且,该文明确了模型所用参数的提取方法,其中关键参数获取自器件设计环节,建立起器件设计者与应用者之间的桥梁。最后,对国网智能电网研究院有限公司研制的6.5 kV/400 A SiC MOSFET器件开展短路测试实验,仿真结果与实验结果表现出较好的一致性,短路电流关键特征的相对误差小于2.5%,验证了该行为模型的准确性。
文摘The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.
基金Project supported by the National Natural Science Foundation of China(No.61464002)the Grand Science and Technology Special Project in Guizhou Province of China(No.[2015]6006)the Ministry of Education Open Foundation for Semiconductor Power Device Reliability(No.010201)
文摘Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOS- FETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator （DSPSOI） layers. Results show that the safety operation area （SOA） of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV-cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.
文摘The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.
基金Project supported by the National Natural Science Foundation of China(Nos.60906037,60906038)the Fundamental Research Funds for the Central Universities,China(Nos.ZYGX2009J027,E022050205)the Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices
文摘A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region.At OFF state,the low-k dielectric trench（LDT） can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time,the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally,ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics,such as low gateto -drain charge density（〈 0.6 nC/mm^2） and a robust safe operating area（0-84 V）.
