针对传统反应扩散(reaction-diffusion,R-D)机制不适合纳米互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)集成电路正偏置温度不稳定性(positive bias temperature instability,PBTI)老化效应分析的问题,文章采...针对传统反应扩散(reaction-diffusion,R-D)机制不适合纳米互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)集成电路正偏置温度不稳定性(positive bias temperature instability,PBTI)老化效应分析的问题,文章采用电荷俘获-释放(trapping-detrapping,T-D)机制,结合线性分析和数据拟合方法,建立了N型金属氧化物半导体(negative channel metal oxide semiconductor,NMOS)管PBTI效应引起的基本逻辑门单元的时延退化预测模型。仿真实验结果表明,采用该模型的电路PBTI老化预测结果与HSpice软件仿真得到的时延预测结果相比,平均误差为2%;关键路径时序余量评估实验表明,与基于R-D机制的老化时延模型相比,在相同的电路生命周期要求下,该模型需要的时序余量更小。展开更多
The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy di...The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.展开更多
The influence of positive bias temperature instability(PBTI)on 1/f noise performance is systematically investigated on n-channel fin field-effect transistor(FinFET).The FinFET with long and short channel(L=240 nm,16 n...The influence of positive bias temperature instability(PBTI)on 1/f noise performance is systematically investigated on n-channel fin field-effect transistor(FinFET).The FinFET with long and short channel(L=240 nm,16 nm respectively)is characterized under PBTI stress from 0 s to 104 s.The 1/f noise features are analyzed by using the unified physical model taking into account the contributions from the carrier number and channel mobility fluctuations.The I d-V g,I d-V d,I g-V g tests are conducted to support and verify the physical analysis in the PBTI process.It is found that the influence of the channel mobility fluctuations may not be neglected.Due to the mobility degradation in a short-channel device,the noise level of the short channel device also degrades.Trapping and trap generation regimes of PBTI occur in high-k layer and are identified based on the results obtained for the gate leakage current and 1/f noise.展开更多
A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power ga...A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.展开更多
Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all de...Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.展开更多
Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage sh...Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.展开更多
文摘针对传统反应扩散(reaction-diffusion,R-D)机制不适合纳米互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)集成电路正偏置温度不稳定性(positive bias temperature instability,PBTI)老化效应分析的问题,文章采用电荷俘获-释放(trapping-detrapping,T-D)机制,结合线性分析和数据拟合方法,建立了N型金属氧化物半导体(negative channel metal oxide semiconductor,NMOS)管PBTI效应引起的基本逻辑门单元的时延退化预测模型。仿真实验结果表明,采用该模型的电路PBTI老化预测结果与HSpice软件仿真得到的时延预测结果相比,平均误差为2%;关键路径时序余量评估实验表明,与基于R-D机制的老化时延模型相比,在相同的电路生命周期要求下,该模型需要的时序余量更小。
基金Project supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.
基金Project supported by the National Natural Science Foundation of China(Grant No.61634008).
文摘The influence of positive bias temperature instability(PBTI)on 1/f noise performance is systematically investigated on n-channel fin field-effect transistor(FinFET).The FinFET with long and short channel(L=240 nm,16 nm respectively)is characterized under PBTI stress from 0 s to 104 s.The 1/f noise features are analyzed by using the unified physical model taking into account the contributions from the carrier number and channel mobility fluctuations.The I d-V g,I d-V d,I g-V g tests are conducted to support and verify the physical analysis in the PBTI process.It is found that the influence of the channel mobility fluctuations may not be neglected.Due to the mobility degradation in a short-channel device,the noise level of the short channel device also degrades.Trapping and trap generation regimes of PBTI occur in high-k layer and are identified based on the results obtained for the gate leakage current and 1/f noise.
基金Projects(60873016, 61170083) supported by the National Natural Science Foundation of ChinaProject(20114307110001) supported by the Doctoral Fund of Ministry of Education of China
文摘A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）, the Program for New Century Excellent Talents of Ministry of Education of China （Grant No 681231366）, the National Defense Pre-Research Foundation of China （Grant No 51308040103） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.
基金Project supported by the Important National Science&Technology Specific Projects(No.2009ZX02035)the National Natural Science Foundation of China(Nos.61176091,61306129)
文摘Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.
