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Degradation characteristics and mechanism of PMOSFETs under NBT-PBT-NBT stress

Degradation characteristics and mechanism of PMOSFETs under NBT-PBT-NBT stress
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摘要 Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature (NBT-PBT-NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion. Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature (NBT-PBT-NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2007年第5期1445-1449,共5页 中国物理B(英文版)
基金 Project supported by the National Natural Science Foundation of China (Grant No 60206006), the Program for New Century Excellent Talents of Ministry of Education of China (Grant No 681231366), the National Defense Pre-Research Foundation of China (Grant No 51308040103) and the Key Project of Chinese Ministry of Education (Grant No 104172).
关键词 ultra deep submicron PMOSFETs negative bias temperature instability (NBTI) positive bias temperature instability (PBTI) interface traps ultra deep submicron PMOSFETs, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), interface traps
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参考文献11

  • 1Jeppson K O and Svensson C M 2004 J. Appl. Phys. 48 1977
  • 2Varghese D, Mahapatra S and Alam M A 2005 IEEE Electron Device Letters 26 572
  • 3Kimizuka N, Yamaguchi K, Imai K, Iizuka T, Liu C T, Keller R C and Horiuchi T 2000 Symposium on VLSI Technology p92
  • 4Young Jomi A, Hye Jin C, Hee Soo K, Choong H L, Choi L, Jacman Y, Tac Y K, Eno S C, Suk K S, Donggun P, Kinam K and Byung-I1 R 2005 International Reliability Physics Symposium p352
  • 5Li E, Rosenbaum E, Register L F, Tao J and Fang P 2000 International Reliability Physics Symposium p103
  • 6Liu H X, Hao Y, Peaker A R and Hawinks I 2005 Chin. Phys. 14 1644
  • 7Cheung K P 2003 Appl. Phys. Lett. 83 2400
  • 8Schroder D K and Babcock J A 2003 J. Appl. Phys. 94 1
  • 9Ogawa S and Shiono N 1995 Phys. Rev. B 51 4218
  • 10Li J, Liu H X and Hao Y 2006 Acta Phys. Sin. 55 2508 (in Chinese)

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