A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VD...A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.展开更多
To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the infl...To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.展开更多
In power electronics applications,the selection of condition monitoring methods significantly affects both the precision and complexity of the junction temperature evaluation,which is essential for the reliability ass...In power electronics applications,the selection of condition monitoring methods significantly affects both the precision and complexity of the junction temperature evaluation,which is essential for the reliability assessment of power semiconductor devices.This study begins with a failure mechanism analysis of state-of-the-art power semiconductor devices.Junction temperature measurement methods can be categorized into three distinct approaches:thermal image-based,thermal model-based,and temperature-sensitive electrical parameter(TSEP)-based methods.Their respective advantages and disadvantages are comprehensively compared.Moreover,condition monitoring of the ON-state voltage drop is summarized and benchmarked.ON-state voltage and junction temperature measurements are experimentally demonstrated in a standard three-phase converter,which provides superior measurement accuracy and rapid dynamic response characteristics.Additionally,this investigation is extended to measurement methods for TSEP in wide-bandgap semiconductors.展开更多
The aim of this study is to achieve online monitoring of the junction temperature of double-sided-cooling insulated gate bipolar transistor(IGBT)power modules by using the on-state voltage under a high current to maxi...The aim of this study is to achieve online monitoring of the junction temperature of double-sided-cooling insulated gate bipolar transistor(IGBT)power modules by using the on-state voltage under a high current to maximize the utilization of IGBT power chips.Online junction temperature measurement plays an important role in improving the reliability of the inverter with IGBT,increasing the power density of the motor controller of electric vehicles,and reducing the cost of electric vehicles.展开更多
Dielectric engineering plays a crucial role in the process of device miniaturization.Herein we investigate the electrical properties of bilayer GaSe metal-oxide-semiconductor field-effect transistors(MOSFETs),consider...Dielectric engineering plays a crucial role in the process of device miniaturization.Herein we investigate the electrical properties of bilayer GaSe metal-oxide-semiconductor field-effect transistors(MOSFETs),considering hetero-gate-dielectric construction,dielectric materials and GaSe stacking pattern.The results show that device performance strongly depends on the dielectric constants and locations of insulators.When highk dielectric is placed close to the drain,it behaves with a larger on-state current(I_(on))of 5052μA/μm when the channel is 5 nm.Additionally,when the channel is 5 nm and insulator is HfO_(2),the largest I_(on) is 5134μA/μm for devices with AC stacking GaSe channel.In particular,when the gate length is 2 nm,it still meets the HP requirements of ITRS 2028 for the device with AA stacking when high-k dielectric is used.Hence,the work provides guidance to regulate the performance of the two-dimensional nanodevices by dielectric engineering.展开更多
目的:分析对产妇开展自由体位联合基于温柔分娩理念的一对一陪伴式助产护理的效果。方法:将2024年2—11月于无锡市妇幼保健院分娩的106例产妇随机分为对照组(n=53,接受常规分娩护理)与观察组(n=53,实施自由体位联合基于温柔分娩理念的...目的:分析对产妇开展自由体位联合基于温柔分娩理念的一对一陪伴式助产护理的效果。方法:将2024年2—11月于无锡市妇幼保健院分娩的106例产妇随机分为对照组(n=53,接受常规分娩护理)与观察组(n=53,实施自由体位联合基于温柔分娩理念的一对一陪伴式助产护理)。对比两组护理效果。结果:与对照组相比,观察组剖宫产率、产后出血率更低,第一产程、第二产程、第三产程时间更短(P<0.05)。两组新生儿窒息发生率、出生1 min Apgar评分比较,无统计学差异(P>0.05)。与护理前相比,两组产妇护理后的焦虑、抑郁评分较护理前低,且与对照组相比,观察组更低(P<0.05)。结论:自由体位联合基于温柔分娩理念的一对一陪伴式助产护理可降低产妇剖宫产率、产后出血率,缩短产程,改善产妇心理状态。展开更多
In vertical channel transistors(VCTs),source/drain ion implantation(I/I)represents a significant technical challenge due to inherent three-dimensional structural constraints,which induce complications such as difficul...In vertical channel transistors(VCTs),source/drain ion implantation(I/I)represents a significant technical challenge due to inherent three-dimensional structural constraints,which induce complications such as difficulties in dummy gate forma-tion and shadowing effects of I/I.This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation.It reveals the significant role of the lightly doped regions(LDRs)naturally formed due to ion implantation in source/drain of VCTs.Furthermore,it was found that VCT with-out dummy gates can achieve an approximately 27%increase in on-state current(Ion)under the same implantation conditions,and can greatly simplify the process flow and reduce costs.Finally,N-type and P-type VCTs were successfully fabricated using this implantation method.展开更多
基金Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province,China(Grant No.2018JC-017)111 Project(Grant No.B12026)。
文摘A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.
基金Project supported by the Key Research and Development Program of Shaanxi(Grant No.2021GY-010)the National Defense Science and Technology Foundation Strengthening Program of China(Grant No.2019-XXXX-XX-236-00).
文摘To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.
文摘In power electronics applications,the selection of condition monitoring methods significantly affects both the precision and complexity of the junction temperature evaluation,which is essential for the reliability assessment of power semiconductor devices.This study begins with a failure mechanism analysis of state-of-the-art power semiconductor devices.Junction temperature measurement methods can be categorized into three distinct approaches:thermal image-based,thermal model-based,and temperature-sensitive electrical parameter(TSEP)-based methods.Their respective advantages and disadvantages are comprehensively compared.Moreover,condition monitoring of the ON-state voltage drop is summarized and benchmarked.ON-state voltage and junction temperature measurements are experimentally demonstrated in a standard three-phase converter,which provides superior measurement accuracy and rapid dynamic response characteristics.Additionally,this investigation is extended to measurement methods for TSEP in wide-bandgap semiconductors.
基金Supported by the National Key Research and Development Program of China(2016YFB0100600).
文摘The aim of this study is to achieve online monitoring of the junction temperature of double-sided-cooling insulated gate bipolar transistor(IGBT)power modules by using the on-state voltage under a high current to maximize the utilization of IGBT power chips.Online junction temperature measurement plays an important role in improving the reliability of the inverter with IGBT,increasing the power density of the motor controller of electric vehicles,and reducing the cost of electric vehicles.
基金supported by the National Natural Science Foundation of China(Grants Nos.12374070 and 12074103)the Foundation for University Key Young Teacher of Henan(Grant No.2023GGJS035)+2 种基金Henan Province Postdoctoral Project Launch Funding(Grant No.5201029430112)the Science and Technology Program of Henan(Grant No.232102230080)supported by the High Performance Computing Center of Henan Normal University.
文摘Dielectric engineering plays a crucial role in the process of device miniaturization.Herein we investigate the electrical properties of bilayer GaSe metal-oxide-semiconductor field-effect transistors(MOSFETs),considering hetero-gate-dielectric construction,dielectric materials and GaSe stacking pattern.The results show that device performance strongly depends on the dielectric constants and locations of insulators.When highk dielectric is placed close to the drain,it behaves with a larger on-state current(I_(on))of 5052μA/μm when the channel is 5 nm.Additionally,when the channel is 5 nm and insulator is HfO_(2),the largest I_(on) is 5134μA/μm for devices with AC stacking GaSe channel.In particular,when the gate length is 2 nm,it still meets the HP requirements of ITRS 2028 for the device with AA stacking when high-k dielectric is used.Hence,the work provides guidance to regulate the performance of the two-dimensional nanodevices by dielectric engineering.
文摘目的:分析对产妇开展自由体位联合基于温柔分娩理念的一对一陪伴式助产护理的效果。方法:将2024年2—11月于无锡市妇幼保健院分娩的106例产妇随机分为对照组(n=53,接受常规分娩护理)与观察组(n=53,实施自由体位联合基于温柔分娩理念的一对一陪伴式助产护理)。对比两组护理效果。结果:与对照组相比,观察组剖宫产率、产后出血率更低,第一产程、第二产程、第三产程时间更短(P<0.05)。两组新生儿窒息发生率、出生1 min Apgar评分比较,无统计学差异(P>0.05)。与护理前相比,两组产妇护理后的焦虑、抑郁评分较护理前低,且与对照组相比,观察组更低(P<0.05)。结论:自由体位联合基于温柔分娩理念的一对一陪伴式助产护理可降低产妇剖宫产率、产后出血率,缩短产程,改善产妇心理状态。
文摘In vertical channel transistors(VCTs),source/drain ion implantation(I/I)represents a significant technical challenge due to inherent three-dimensional structural constraints,which induce complications such as difficulties in dummy gate forma-tion and shadowing effects of I/I.This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation.It reveals the significant role of the lightly doped regions(LDRs)naturally formed due to ion implantation in source/drain of VCTs.Furthermore,it was found that VCT with-out dummy gates can achieve an approximately 27%increase in on-state current(Ion)under the same implantation conditions,and can greatly simplify the process flow and reduce costs.Finally,N-type and P-type VCTs were successfully fabricated using this implantation method.
