Highly oriented voids-free 3C-SiC heteroepitaxial layers are grown onφ50mm Si (100) substrates by low pressure chemical vapor deposition (LPCVD).The initial stage of carbonization and the surface morphology of carbon...Highly oriented voids-free 3C-SiC heteroepitaxial layers are grown onφ50mm Si (100) substrates by low pressure chemical vapor deposition (LPCVD).The initial stage of carbonization and the surface morphology of carbonization layers of Si (100) are studied using reflection high energy electron diffraction (RHEED) and scanning electron microscopy (SEM).It is shown that the optimized carbonization temperature for the growth of voids-free 3C-SiC on Si (100) substrates is 1100℃.The electrical properties of SiC layers are characterized using Van der Pauw method.The I-V,C-V,and the temperature dependence of I-V characteristics in n-3C-SiC/p-Si heterojunctions with AuGeNi and Al electrical pads are investigated.It is shown that the maximum reverse breakdown voltage of the n-3C-SiC/p-Si heterojunction diodes reaches to 220V at room temperature.These results indicate that the SiC/Si heterojunction diode can be used to fabricate the wide bandgap emitter SiC/Si heterojunction bipolar transistors (HBT's).展开更多
A method to improve Ge n＋/p junction diode performance by excimer laser annealing （ELA） and epitaxial Si passi- vation under a low ion implantation dose is demonstrated. The epitaxial Si passivation layer can unpin...A method to improve Ge n＋/p junction diode performance by excimer laser annealing （ELA） and epitaxial Si passi- vation under a low ion implantation dose is demonstrated. The epitaxial Si passivation layer can unpin the Fermi level of the contact of Al/n-Ge to some extent and reduce the contact resistance. In addition, the fabricated Ge n ：/p junction diode by ELA plus epitaxial Si passivation exhibits a decreased reverse current density and an increased forward current density, resulting in a rectification ratio of about 6.5 x 10^6 beyond two orders magnitude larger than that by ELA alone. The reduced specific contact resistivity of metal on n-doped germanium and well-behaved germanium n＋/p diode arc beneficial for the performance improvement of Ge n-MOSFETs and other opto-electronic devices.展开更多
We report the performances of a chalcopyrite Cu(In, Ga)Se<sub>2 </sub>CIGS-based thin-film solar cell with a newly employed high conductive n-Si layer. The data analysis was performed with the help of the ...We report the performances of a chalcopyrite Cu(In, Ga)Se<sub>2 </sub>CIGS-based thin-film solar cell with a newly employed high conductive n-Si layer. The data analysis was performed with the help of the 1D-Solar Cell Capacitance Simulator (1D-SCAPS) software program. The new device structure is based on the CIGS layer as the absorber layer, n-Si as the high conductive layer, i-In<sub>2</sub>S<sub>3</sub>, and i-ZnO as the buffer and window layers, respectively. The optimum CIGS bandgap was determined first and used to simulate and analyze the cell performance throughout the experiment. This analysis revealed that the absorber layer’s optimum bandgap value has to be 1.4 eV to achieve maximum efficiency of 22.57%. Subsequently, output solar cell parameters were analyzed as a function of CIGS layer thickness, defect density, and the operating temperature with an optimized n-Si layer. The newly modeled device has a p-CIGS/n-Si/In<sub>2</sub>S<sub>3</sub>/Al-ZnO structure. The main objective was to improve the overall cell performance while optimizing the thickness of absorber layers, defect density, bandgap, and operating temperature with the newly employed optimized n-Si layer. The increase of absorber layer thickness from 0.2 - 2 µm showed an upward trend in the cell’s performance, while the increase of defect density and operating temperature showed a downward trend in solar cell performance. This study illustrates that the proposed cell structure shows higher cell performances and can be fabricated on the lab-scale and industrial levels.展开更多
文摘Highly oriented voids-free 3C-SiC heteroepitaxial layers are grown onφ50mm Si (100) substrates by low pressure chemical vapor deposition (LPCVD).The initial stage of carbonization and the surface morphology of carbonization layers of Si (100) are studied using reflection high energy electron diffraction (RHEED) and scanning electron microscopy (SEM).It is shown that the optimized carbonization temperature for the growth of voids-free 3C-SiC on Si (100) substrates is 1100℃.The electrical properties of SiC layers are characterized using Van der Pauw method.The I-V,C-V,and the temperature dependence of I-V characteristics in n-3C-SiC/p-Si heterojunctions with AuGeNi and Al electrical pads are investigated.It is shown that the maximum reverse breakdown voltage of the n-3C-SiC/p-Si heterojunction diodes reaches to 220V at room temperature.These results indicate that the SiC/Si heterojunction diode can be used to fabricate the wide bandgap emitter SiC/Si heterojunction bipolar transistors (HBT's).
基金Project supported by the High Level Talent Project of Xiamen University of Technology,China(Grant No.YKJ16012R)
文摘A method to improve Ge n＋/p junction diode performance by excimer laser annealing （ELA） and epitaxial Si passi- vation under a low ion implantation dose is demonstrated. The epitaxial Si passivation layer can unpin the Fermi level of the contact of Al/n-Ge to some extent and reduce the contact resistance. In addition, the fabricated Ge n ：/p junction diode by ELA plus epitaxial Si passivation exhibits a decreased reverse current density and an increased forward current density, resulting in a rectification ratio of about 6.5 x 10^6 beyond two orders magnitude larger than that by ELA alone. The reduced specific contact resistivity of metal on n-doped germanium and well-behaved germanium n＋/p diode arc beneficial for the performance improvement of Ge n-MOSFETs and other opto-electronic devices.
文摘We report the performances of a chalcopyrite Cu(In, Ga)Se<sub>2 </sub>CIGS-based thin-film solar cell with a newly employed high conductive n-Si layer. The data analysis was performed with the help of the 1D-Solar Cell Capacitance Simulator (1D-SCAPS) software program. The new device structure is based on the CIGS layer as the absorber layer, n-Si as the high conductive layer, i-In<sub>2</sub>S<sub>3</sub>, and i-ZnO as the buffer and window layers, respectively. The optimum CIGS bandgap was determined first and used to simulate and analyze the cell performance throughout the experiment. This analysis revealed that the absorber layer’s optimum bandgap value has to be 1.4 eV to achieve maximum efficiency of 22.57%. Subsequently, output solar cell parameters were analyzed as a function of CIGS layer thickness, defect density, and the operating temperature with an optimized n-Si layer. The newly modeled device has a p-CIGS/n-Si/In<sub>2</sub>S<sub>3</sub>/Al-ZnO structure. The main objective was to improve the overall cell performance while optimizing the thickness of absorber layers, defect density, bandgap, and operating temperature with the newly employed optimized n-Si layer. The increase of absorber layer thickness from 0.2 - 2 µm showed an upward trend in the cell’s performance, while the increase of defect density and operating temperature showed a downward trend in solar cell performance. This study illustrates that the proposed cell structure shows higher cell performances and can be fabricated on the lab-scale and industrial levels.
