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Cache performance optimization of irregular sparse matrix multiplication on modern multi-core CPU and GPU
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作者 刘力 LiuLi Yang Guang wen 《High Technology Letters》 EI CAS 2013年第4期339-345,共7页
This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the ... This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the multiplier-matrix,and the other is caused by the multiplicand.For each of them,the paper puts forward an optimization method respectively.The first hash based method removes cache misses of the 1 st category effectively,and improves the performance by a factor of 6 on an Intel 8-core CPU for the best cases.For cache misses of the 2nd category,it proposes a new cache replacement algorithm,which achieves a cache hit rate much higher than other historical knowledge based algorithms,and the algorithm is applicable on CELL and GPU.To further verify the effectiveness of our methods,we implement our algorithm on GPU,and the performance perfectly scales with the size of on-chip storage. 展开更多
关键词 sparse matrix multiplication cache miss SCALABILITY multi-core cpu GPU
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Preparation and sustained release performance of multi-core capsules based on fragrance-loaded Pickering emulsions
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作者 Xinyi Liu Juanbo Chen +4 位作者 Haoyue Hou Jiawei Hou Meiling Shi Sa Zeng Tao Meng 《日用化学工业(中英文)》 北大核心 2025年第3期286-294,共9页
Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragran... Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragranceloaded capsules.In this work,the natural materials sodium alginate and gelatine are dissolved and act as the aqueous phase,lavender is dissolved in caprylic/capric triglyceride(GTCC)as the oil phase,and SiO_(2) nanoparticles with neutralwettability as a solid emulsifier to form O/W Pickering emulsions simultaneously.Finally,multi-core capsules are prepared using the drop injection method with emulsions as templates.The results show that the capsules have been successfully prepared with a spherical morphology and multi-core structure,and the encapsulation rate of multi-core capsules can reach up to 99.6%.In addition,the multi-core capsules possess desirable sustained release performance,the cumulative sustained release rate of fragrance at 25℃over 49 days is only 32.5%.It is attributed to the significant protection of multi-core structure,Pickering emulsion nanoparticle membranes,and hydrogel network shell for encapsulated fragrance.This study is designed to deliver a new strategy for using sustained-release technology with fragrance in food,cosmetics,textiles,and other fields. 展开更多
关键词 FRAGRANCE Pickering emulsion multi-core capsules encapsulation efficiency sustained release
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关键核心技术国产替代的创新模式研究——基于CPU技术头部企业的双案例分析 被引量:6
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作者 王砚羽 卢婷 刘汝芳 《科学学研究》 北大核心 2025年第4期712-722,750,共12页
关键核心技术是国之重器。本研究以龙芯中科和天津飞腾两家CPU技术头部企业为案例,探讨关键核心技术国产替代的创新模式。得出如下结论:(1)识别出关键核心技术国产替代的两种路径,龙芯中科采用“技术引进+学习导向的消化吸收”路径,最... 关键核心技术是国之重器。本研究以龙芯中科和天津飞腾两家CPU技术头部企业为案例,探讨关键核心技术国产替代的创新模式。得出如下结论:(1)识别出关键核心技术国产替代的两种路径,龙芯中科采用“技术引进+学习导向的消化吸收”路径,最终实现了核心技术自主可控;而天津飞腾采用“技术引进+应用导向的消化吸收”路径,存在卡脖子风险。(2)不同的国产替代创新模式塑造了不同的企业技术能力和生态能力。本研究为理解技术限制背景下的技术主权提供了新的视角,为政策制定者和行业利益相关者提供管理启示。 展开更多
关键词 关键核心技术 国产替代 创新模式 案例研究 cpu芯片
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面向特定应用的可配置CPU性能分析方法
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作者 邓全 林荣臻 +2 位作者 罗莉 鲁建壮 王永文 《计算机工程与科学》 北大核心 2025年第11期1901-1911,共11页
随着集成电路的发展和芯片应用的不断拓展,可配置CPU为芯片设计空间的探索提供了便利。可配置CPU不仅能满足敏捷设计的需求,还能兼顾用户根据目标应用进行调优的需求。然而,目前面向特定应用的可配置CPU的性能调优仍主要依赖于资深体系... 随着集成电路的发展和芯片应用的不断拓展,可配置CPU为芯片设计空间的探索提供了便利。可配置CPU不仅能满足敏捷设计的需求,还能兼顾用户根据目标应用进行调优的需求。然而,目前面向特定应用的可配置CPU的性能调优仍主要依赖于资深体系结构工程师,缺乏一套科学方法进行指导,因此,提出了一种面向特定应用的可配置CPU性能分析方法。在软件层面,利用Perf工具快速定位应用程序在硬件执行时的热点代码块;在硬件层面,通过分析框架的2种计数模式(时钟周期计数与slots计数),锁定各个执行部件的热点执行情况,以便设计人员快速定位硬件执行的热点行为。对支持RISCV指令集的可配置DMR架构在流体力学典型程序NPB上进行了敏捷设计。实验结果表明,迭代后可配置CPU单核性能提升了13.2%,面积开销增加了12.2%。 展开更多
关键词 性能分析 可配置cpu PMU NPB 测试
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基于CPU-GPU的超音速流场N-S方程数值模拟
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作者 卢志伟 张皓茹 +3 位作者 刘锡尧 王亚东 张卓凯 张君安 《中国机械工程》 北大核心 2025年第9期1942-1950,共9页
为深入分析超音速流场的特性并提高数值计算效率,设计了一种高效的加速算法。该算法充分利用中央处理器-图形处理器(CPU-GPU)异构并行模式,通过异步流方式实现数据传输及处理,显著加速了超音速流场数值模拟的计算过程。结果表明:GPU并... 为深入分析超音速流场的特性并提高数值计算效率,设计了一种高效的加速算法。该算法充分利用中央处理器-图形处理器(CPU-GPU)异构并行模式,通过异步流方式实现数据传输及处理,显著加速了超音速流场数值模拟的计算过程。结果表明:GPU并行计算速度明显高于CPU串行计算速度,其加速比随流场网格规模的增大而明显提高。GPU并行计算可以有效提高超音速流场的计算速度,为超音速飞行器的设计、优化、性能评估及其研发提供一种强有力的并行计算方法。 展开更多
关键词 超音速流场 中央处理器-图形处理器 异构计算 有限差分
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基于多核CPU的雷达导引头数字化实时仿真研究 被引量:2
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作者 苏灏杨 夏伟杰 +1 位作者 吴雪 王宇 《遥测遥控》 2025年第2期92-99,共8页
雷达导引头仿真系统在导引头精确打击目标的过程中起着重要的作用。随着仿真系统的复杂度不断提升以及数据处理需求的日益增长,传统的串行计算仿真技术已难以满足雷达导引头数字仿真系统对实时性的严格要求。针对现有雷达导引头仿真过... 雷达导引头仿真系统在导引头精确打击目标的过程中起着重要的作用。随着仿真系统的复杂度不断提升以及数据处理需求的日益增长,传统的串行计算仿真技术已难以满足雷达导引头数字仿真系统对实时性的严格要求。针对现有雷达导引头仿真过程中耗时过长的问题,本文提出了一种全流程的数字化实时仿真方法。首先,将传统全流程仿真架构的核心部分——接收控制系统指令、接收回波仿真数据、SAR(Synthetic aperture Radar,合成孔径雷达)成像处理、成像结果上传与界面动态更新进行流水并行化。其次,利用OpenMP(开放式多处理)多核并行模型,对SAR成像算法主要步骤进行多核CPU(Central Processing Unit,中央处理器)并行处理。然后,引入高性能数学计算库FFTW3(西方最快傅里叶变换第3版)快速实现成像算法的傅里叶变换,加快SAR成像算法处理速度。最后仿真结果表明:该全流程的设计方法相较于传统的串行仿真,加速比达到100倍左右,同时加速前后的SAR图像相似度接近于1。在处理精度和效果一致的前提下,该方法能够完成雷达导引头系统的全流程实时仿真,具有较好的工程应用前景。 展开更多
关键词 雷达导引头 SAR仿真 多核cpu 并行计算 实时仿真
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基于CPU-FPGA的SoC实验系统设计
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作者 王丽杰 钱俊宏 +4 位作者 何俊峰 王蕊 贺媛 刘凤敏 张彤 《吉林大学学报(信息科学版)》 2025年第3期518-523,共6页
针对现有微电子与集成电路专业课程大多以理论为主,缺少仿真实验,FPGA(Field Progra mmable Gate Array)实操类实验项目严重不足的问题,设计了一套基于CPU(Central Processing Unit)-FPGA的SoC(System on Chip)实验系统。利用ModelSim... 针对现有微电子与集成电路专业课程大多以理论为主,缺少仿真实验,FPGA(Field Progra mmable Gate Array)实操类实验项目严重不足的问题,设计了一套基于CPU(Central Processing Unit)-FPGA的SoC(System on Chip)实验系统。利用ModelSim等仿真工具,以FPGA为开发平台实现CPU系统功能。以RISC-V(Reduced Instruction Set Computer)精简指令集为该CPU的指令集,以模块化为设计思想,从微处理器的局部到总体设计5级流水线CPU。系统融合了软硬件开发,能激发学生的学习兴趣。搭建的实验平台逐步实现CPU的配置与指令集至整个CPU的架构、编程、仿真、下载与调试,使学生对FPGA实现集成电路系统设计有深入理解,有助于专业理论课程的学习。通过将OBE(Outcomes-Based Education)教学理论应用于集成电路EDA(Electronic Design Automation)课程的仿真实验结果表明,这种设计方法与内容适用于产学研相结合,并能提高学生创新创业能力。 展开更多
关键词 中央处理器 现场可编程门阵列 实验系统 流水线技术
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Enrichment of Fetal Nucleated Red Blood Cells by Multi-core Magnetic Composite Particles for Non-invasive Prenatal Diagnosis 被引量:1
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作者 PAN Ying WANG Qing +7 位作者 HUANG Wen-jun QIAO Feng-1i LIU Yu-ping ZHANG Yu-cheng HAI De-yang DU Ying,ting WANG Wen-yue ZHANG Ai-chen 《Chemical Research in Chinese Universities》 SCIE CAS CSCD 2012年第3期443-448,共6页
A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor(anti-CD71), was prepared. The fetal nucleated red blo... A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor(anti-CD71), was prepared. The fetal nucleated red blood cells(FNRBCs) in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization(FISH) technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis. 展开更多
关键词 Fetal nucleated red blood cell(FNRBC) Prenatal diagnosis NON-INVASIVE multi-core magnetic compositeparticle
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Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips
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作者 Chengbo Xue Yougen Xu +1 位作者 Yue Hao Wei Gao 《Journal of Beijing Institute of Technology》 EI CAS 2019年第3期497-509,共13页
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti... A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield. 展开更多
关键词 process VARIATION TASK mapping FAULT-TOLERANT network-on-chips multi-core
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Multi-core optimization for conjugate gradient benchmark on heterogeneous processors
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作者 邓林 窦勇 《Journal of Central South University》 SCIE EI CAS 2011年第2期490-498,共9页
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t... Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores. 展开更多
关键词 multi-core processor NAS parallelization CG memory optimization
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Theoretical Analysis on Inter-Core Crosstalk Suppression Model for Multi-Core Fiber
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作者 Jiajing Tu Xueqin Xie Keping Long 《China Communications》 SCIE CSCD 2016年第8期192-197,共6页
Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so ... Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly. 展开更多
关键词 multi-core fiber CROSSTALK mode coupling coefficient
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利用CPU和GPU混合并行方法快速构建海洋扰动重力梯度基准图
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作者 黄炎 李姗姗 +3 位作者 吕明昊 范雕 谭勖立 冯进凯 《武汉大学学报(信息科学版)》 北大核心 2025年第3期515-527,共13页
高精度、高分辨率的海洋扰动重力梯度基准图是将水下扰动重力梯度辅助惯性导航付诸于实践的关键技术之一,可依据边值问题理论,基于移去-恢复技术计算求得。基于传统串行算法存在计算效率低、耗时长等问题,为满足大范围乃至全球海洋扰动... 高精度、高分辨率的海洋扰动重力梯度基准图是将水下扰动重力梯度辅助惯性导航付诸于实践的关键技术之一,可依据边值问题理论,基于移去-恢复技术计算求得。基于传统串行算法存在计算效率低、耗时长等问题,为满足大范围乃至全球海洋扰动重力梯度基准图的快速构建需求,利用中央处理器(central processing unit,CPU)与图形处理器(graph processing unit,GPU)混合并行(CPU+GPU)编程平台,设计了一种高效的混合并行计算方案。首先,利用数组收缩膨胀方法,有效解决了CPU进行勒让德函数递推计算过程中内存读写冲突问题;然后,引入Hilbert空间填充曲线,将二维格网重力异常数据降维成为具有高度聚簇性的一维数组,通过其在GPU显存中的快速索引,实现了Stokes积分的高效计算。在CPU型号为Intel Xeon(R)Gold 6130、GPU型号为Tesla V100的计算机上进行实验,利用该混合并行方案计算6°×6°范围、1′分辨率的全张量海洋扰动重力梯度基准图仅需15.84 s,而传统串行方法需要35 min以上;计算2°×2°范围、30″分辨率基准图仅需22.7 s,串行方法则需要52 min;计算2°×2°范围、10″分辨率基准图需要26.7 min,串行方法则需要两天以上。在保证并行计算绝对误差小于等于1×10^(-6) E、T_(xx)+T_(yy)+T_(zz)绝对值的最大值小于0.1 E、均方根误差小于0.01 E的前提下,实现了全球全张量海洋扰动重力梯度基准图模型的快速构建。 展开更多
关键词 扰动重力梯度 边值问题 cpu GPU 混合并行
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Parallel scheduling strategy of web-based spatial computing tasks in multi-core environment
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作者 郭明强 Huang Ying Xie Zhong 《High Technology Letters》 EI CAS 2014年第4期395-400,共6页
In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of pa... In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of parallel processing mechanisms.One is that it can evenly allocate tasks to each server node in the cluster and the other is that it can implement the load balancing inside a server node.Based on the strategy,a new web-based spatial computing model is designed in this paper,in which,a task response ratio calculation method,a request queue buffer mechanism and a thread scheduling strategy are focused on.Experimental results show that the new model can fully use the multi-core computing advantage of each server node in the concurrent access environment and improve the average hits per second,average I/O Hits,CPU utilization and throughput.Using speed-up ratio to analyze the traditional model and the new one,the result shows that the new model has the best performance.The performance of the multi-core server nodes in the cluster is optimized;the resource utilization and the parallel processing capabilities are enhanced.The more CPU cores you have,the higher parallel processing capabilities will be obtained. 展开更多
关键词 parallel scheduling strategy the web-based spatial computing model multi-core environment load balancing
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Modeling of Few-Mode Multi-Core Optical Fiber Channel Based on Non-Uniform Mode Field Distribution
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作者 Hang Zhou Bo Liu +6 位作者 Fu Wang Dandan Song Li Li Xiangjun Xin Qinghua Tian Qi Zhang Feng Tian 《China Communications》 SCIE CSCD 2016年第8期184-191,共8页
In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are car... In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results. 展开更多
关键词 few-mode multi-core optical fiber channel non-uniform channel channel modeling
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基于强化学习的负载感知CPU资源分配和管理方法
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作者 许荣飞 苏志远 +1 位作者 麻付强 吴保锡 《计算机技术与发展》 2025年第10期81-88,共8页
随着CPU核的数量增多,合理分配CPU核对于降低系统功耗具有重要意义,如何根据系统运行时的负载情况进行精准的CPU资源分配和管理是一个关键的问题。现在处理器设计提供了很多对功耗优化的机制(比如动态电压频率调整DVFS),但是要让这些机... 随着CPU核的数量增多,合理分配CPU核对于降低系统功耗具有重要意义,如何根据系统运行时的负载情况进行精准的CPU资源分配和管理是一个关键的问题。现在处理器设计提供了很多对功耗优化的机制(比如动态电压频率调整DVFS),但是要让这些机制发挥作用,只有芯片的支持是不够的,还需要软硬协同设计。当前缺乏基于软件来最大化利用这些硬件机制的手段。近年来,机器学习在各个领域展现出巨大的潜力,很多基于机器学习的研究工作应运而生。其中,强化学习具有较强的自适应性,适用于动态感知系统环境并进行资源管理。因此,该文提出了一种基于强化学习的负载感知CPU资源分配和管理方法——RLWAM。该方法提出基于最小原则根据系统中运行时的任务负载进行CPU资源分配和管理,基于强化学习提出了面向上述场景的Q-Learning算法,包括面向任务和系统的状态建模方式、面向绑核、调频和资源整合的动作空间和激励函数,从而帮助系统进一步降低功耗。最后,通过在真实平台上从单类型任务上的绑核调频和多类型任务上的资源整合两个场景对该方法进行实验验证,结果表明该方法具有显著的有效性和可扩展性。 展开更多
关键词 负载感知 强化学习 多核系统 cpu资源分配管理 绑核调频
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Hybridization of Metaheuristics Based Energy Efficient Scheduling Algorithm for Multi-Core Systems
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作者 J.Jean Justus U.Sakthi +4 位作者 K.Priyadarshini B.Thiyaneswaran Masoud Alajmi Marwa Obayya Manar Ahmed Hamza 《Computer Systems Science & Engineering》 SCIE EI 2023年第1期205-219,共15页
The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,... The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,working environments,topologies,and so on.The existing multi-core technology unlocks additional research opportunities for energy minimization by the use of effective task scheduling.At the same time,the task scheduling process is yet to be explored in the multi-core systems.This paper presents a new hybrid genetic algorithm(GA)with a krill herd(KH)based energy-efficient scheduling techni-que for multi-core systems(GAKH-SMCS).The goal of the GAKH-SMCS tech-nique is to derive scheduling tasks in such a way to achieve faster completion time and minimum energy dissipation.The GAKH-SMCS model involves a multi-objectivefitness function using four parameters such as makespan,processor utilization,speedup,and energy consumption to schedule tasks proficiently.The performance of the GAKH-SMCS model has been validated against two datasets namely random dataset and benchmark dataset.The experimental outcome ensured the effectiveness of the GAKH-SMCS model interms of makespan,pro-cessor utilization,speedup,and energy consumption.The overall simulation results depicted that the presented GAKH-SMCS model achieves energy effi-ciency by optimal task scheduling process in MCS. 展开更多
关键词 Task scheduling energy efficiency multi-core systems fitness function MAKESPAN
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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture
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作者 Allam Abumwais Mahmoud Obaid 《Computers, Materials & Continua》 SCIE EI 2023年第3期4951-4963,共13页
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc... Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors. 展开更多
关键词 multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program
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Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors
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作者 Muhammad Ali Ismail 《Computer Technology and Application》 2012年第11期729-733,共5页
In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core proces... In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper. 展开更多
关键词 multi-core memory hierarchy cache access time queuing analysis.
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The Channel Maps and the Position-Velocity Diagrams of Multi-core Structure of Cepheus C
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作者 Yu Zhi yao 1,2 , Jiang Dong rong 1,2 1 (Shanghai Astronomical Observatory, The Chinese Academy of Sciences, Shanghai 200030, China) 2 (National Astronomical Observatories, The Chinese Academy of Sciences, China E mail: zyyu@center. shao. ac. 《天文研究与技术》 CSCD 1999年第S1期218-221,共4页
The first important problem in the star forming process is the formation of proto star core in star forming regions of molecular cloud. The multi core structure in star forming regions is related to the forming of pro... The first important problem in the star forming process is the formation of proto star core in star forming regions of molecular cloud. The multi core structure in star forming regions is related to the forming of proto star core. The molecular radiation of C 18 O( J = 1-0) in Cepheus C has been observed. The C 18 O( J = 1-0) observations form the basis for an interesting study on the cloud cores and star formation activity in the cores of the Cepheus C. In order to study the multi core structure of C 18 O( J = 1-0) in the Cepheus C the channel maps and the position velocity diagrams of C 18 O( J = 1-0) will be shown. From the maps it is found that the contour level and distribution size of the three cores in Cepheus C are related to the channel velocity very much. The channel velocity of C 18 O( J = 1-0) molecules in core b, which distributed in all the channels velocity, is different with one in core a and core c very much. The C 18 O( J = 1-0) molecules in core a and core c of the Cepheus C mostly distributed in the blue shifted channel velocity relating to peak velocity, and only in -10.0 ~ -9.5 km/s, which is the red shifted channel velocity relating to peak velocity. And the contour level of C 18 O( J = 1-0) in -10.0 ~ -9.5 km/s is small and the distrbution size in the channel map is small. According to the position velocity diagrams the asymmetry of the distribution both blue shifted and red shifted components should reflect the asymmetry of the profile. From the diagrams it also is found that the contour level and the distribution size of the three cores are different from each other. Both results from the maps and diagrams are coincident with each other. 展开更多
关键词 MAPS The Channel Maps and the Position-Velocity core Diagrams of multi-core Structure of Cepheus C
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Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on Multi-Core Processor
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作者 Zhang Ziran,Li Jun,Li Changxiao(ZTE Corporation,Shenzhen 518057,P.R.China) 《ZTE Communications》 2009年第1期54-58,共5页
The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Co... The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Consequently,the single-core processor cannot meet the requirements of LTE system.This paper analyzes how to use multi-core processors to achieve parallel processing of uplink demodulation and decoding in LTE systems and designs an approach to parallel processing.The test results prove that this approach works quite well. 展开更多
关键词 CORE LTE Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on multi-core Processor Design
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