As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemente...As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.展开更多
A top-down design methodology is proposed for the design of TFT-LCD one-chip driver ICs,and a 260k color, 176RGB× 220-dot TFT-LCD one-chip driver IC is successfully developed with silicon verification. This IC is...A top-down design methodology is proposed for the design of TFT-LCD one-chip driver ICs,and a 260k color, 176RGB× 220-dot TFT-LCD one-chip driver IC is successfully developed with silicon verification. This IC is a typical mixed-signal VLSI and is implemented by a 0.18μm HV CMOS process. The static power dissipation is about 5mW for 260k color display mode,and the settling time of the output grayscale voltages within 0.2% error is less than 26μs.展开更多
In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）...In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.展开更多
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overh...This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.展开更多
文摘As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.
文摘A top-down design methodology is proposed for the design of TFT-LCD one-chip driver ICs,and a 260k color, 176RGB× 220-dot TFT-LCD one-chip driver IC is successfully developed with silicon verification. This IC is a typical mixed-signal VLSI and is implemented by a 0.18μm HV CMOS process. The static power dissipation is about 5mW for 260k color display mode,and the settling time of the output grayscale voltages within 0.2% error is less than 26μs.
基金Supported by the National High Technology Research and Development Program of China (2006AA01Z226)
文摘In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.
文摘This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.
