This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by t...This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.展开更多
A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard f...A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.展开更多
With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of t...With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source- coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. A-E modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18/tin CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510μm^2 and it can correctly divide within the frequency range of 0.8-9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.展开更多
This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communicatio...This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.展开更多
A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architecture is presented. It exhibits IEEE 802.11 a/b/g （9.5 MHz） and DVB-H （3 MHz, 4 MHz） application. The filter ex...A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architecture is presented. It exhibits IEEE 802.11 a/b/g （9.5 MHz） and DVB-H （3 MHz, 4 MHz） application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 corner frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns （WLAN mode）. Its dissipation is 3.4 mA in RX mode and 2.3 mA （only for one path） in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm^2 and 0.11 mm^2 （calibration circuit excluded）, respectively.展开更多
This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load imp...This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier（TIA）,which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency（RF） ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency（IF） bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure（NF） is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.展开更多
A fully integrated hybrid integer/fractional frequency synthesizer is presented.With a single multiband voltage-controlled-oscillator（VCO）,the frequency synthesizer can support GPS,Galileo,Compass and TDSCDMA standa...A fully integrated hybrid integer/fractional frequency synthesizer is presented.With a single multiband voltage-controlled-oscillator（VCO）,the frequency synthesizer can support GPS,Galileo,Compass and TDSCDMA standards.Design is carefully performed to trade off power,die area and phase noise performance.By reconfiguring between the integer mode and fractional mode,different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously.Moreover,a long sequence length,reduced hardware complexity multi-stage-noise-shaping（MASH）.-.modulator is employed to reduce fractional spur in the fractional mode.Fabricated in a 0.18 m CMOS technology,the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply.The measured phase noise is lower than-80 dBc/Hz at 100 kHz offset and-113 to-124 dBc/Hz at 1 MHz offset respectively,while the measured reference spur is-71 dBc in integer mode and the fractional spur is-65 dBc in fractional mode.展开更多
明确气候变化背景下黑龙江省多尺度干旱时空特征,对于防灾减灾、保障粮食安全至关重要。基于1961—2023年黑龙江省水平分辨率为1°×1°的NCEP(National Center for Environmental Prediction)和GPCC(Global Precipitation ...明确气候变化背景下黑龙江省多尺度干旱时空特征,对于防灾减灾、保障粮食安全至关重要。基于1961—2023年黑龙江省水平分辨率为1°×1°的NCEP(National Center for Environmental Prediction)和GPCC(Global Precipitation Climatology Centre)月尺度格点气象数据,计算不同时间尺度的标准化降水蒸散指数(Standardized Precipitation Evapotranspiration Index,SPEI),使用K-means聚类方法,将黑龙江省分为3个区域,分析1961—2023年黑龙江省不同干旱分区、多时间尺度气象干旱时空特征。结果表明:1961—2023年黑龙江省SPEI指数表现出明显的波动,北部山区4月SPEI呈现显著减小趋势,而中西平原区和东南区在不同时间尺度下SPEI呈增加趋势,表明黑龙江省不同区域的干湿状况存在显著的空间差异。黑龙江省气象干旱主要以大范围群发的形式出现,有两个明显的高发期,分别是1967—1989年和1999—2011年;夏季干旱影响范围普遍大于春季。最近气候期(1991—2020年)黑龙江省的干旱频次增加、强度增强,这一趋势对区域的生态安全和可持续发展构成了挑战。展开更多
基金Supported by the National Nature Science Foundation of China(No.61674037)the Priority Academic Program Development of Jiangsu Higher Education Institutions,the National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.
基金Project supported by the National Natural Science Foundation of China(No.60976023)the National Science and Technology Major Project of China(Nos.2009ZX03007-001,2012ZX03004007-002)
文摘A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.
文摘With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source- coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. A-E modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18/tin CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510μm^2 and it can correctly divide within the frequency range of 0.8-9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.
基金Project supported by the Chinese National High-Tech Research and Development Program(Nos2009ZX03007-001,2009AA011606)the National Natural Science Foundation of China(No60976023)
文摘This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.
文摘A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architecture is presented. It exhibits IEEE 802.11 a/b/g （9.5 MHz） and DVB-H （3 MHz, 4 MHz） application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 corner frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns （WLAN mode）. Its dissipation is 3.4 mA in RX mode and 2.3 mA （only for one path） in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm^2 and 0.11 mm^2 （calibration circuit excluded）, respectively.
基金Project supported by the National Science and Technology Major Project (No.2010ZX03007-002-01)the State Key Development Program for Basic Research of China (No.2010CB327404)
文摘This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier（TIA）,which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency（RF） ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency（IF） bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure（NF） is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.
基金Project supported by the National Science and Technology Major Project,China (No.2010ZX03007-002-01)the State Key Development Program for Basic Research of China (No.2010CB327404)
文摘A fully integrated hybrid integer/fractional frequency synthesizer is presented.With a single multiband voltage-controlled-oscillator（VCO）,the frequency synthesizer can support GPS,Galileo,Compass and TDSCDMA standards.Design is carefully performed to trade off power,die area and phase noise performance.By reconfiguring between the integer mode and fractional mode,different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously.Moreover,a long sequence length,reduced hardware complexity multi-stage-noise-shaping（MASH）.-.modulator is employed to reduce fractional spur in the fractional mode.Fabricated in a 0.18 m CMOS technology,the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply.The measured phase noise is lower than-80 dBc/Hz at 100 kHz offset and-113 to-124 dBc/Hz at 1 MHz offset respectively,while the measured reference spur is-71 dBc in integer mode and the fractional spur is-65 dBc in fractional mode.
