The single-event susceptibility of three silicon carbide(SiC)metal-oxide-semiconductor field-effect transistor(MOSFET)power devices structures(planar,trench and double trench)is researched by the technology computer-a...The single-event susceptibility of three silicon carbide(SiC)metal-oxide-semiconductor field-effect transistor(MOSFET)power devices structures(planar,trench and double trench)is researched by the technology computer-aided design(TCAD)simulation.Comparative analysis of the heavy-ion irradiation effects on three device structures reveals distinct susceptibility characteristics.The gate oxide region is identified as the most sensitive position in planar devices,while trench and doubletrench structures exhibit no localized sensitive regions.Furthermore,the single-event susceptibility demonstrates strong depth dependence across all three structures,with enhanced vulnerability observed at greater ion penetration depths.展开更多
Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain.In this regard,r...Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain.In this regard,reservoir computing(RC)framework,which leverages straightforward training methods and efficient temporal signal processing,has emerged as a promising scheme.While various physical reservoir devices,including ferroelectric,optoelectronic,and memristor-based systems,have been demonstrated,many still face challenges related to compatibility with mainstream complementary metal oxide semiconductor(CMOS)integration processes.This study introduced a silicon-based schottky barrier metal-oxide-semiconductor field effect transistor(SB-MOSFET),which was fabricated under low thermal budget and compatible with back-end-of-line(BEOL).The device demonstrated short-term memory characteristics,facilitated by the modulation of schottky barriers and charge trapping.Utilizing these characteristics,a RC system for temporal data processing was constructed,and its performance was validated in a 5×4 digital classification task,achieving an accuracy exceeding 98%after 50 training epochs.Furthermore,the system successfully processed temporal signal in waveform classification and prediction tasks using time-division multiplexing.Overall,the SB-MOSFET's high compatibility with CMOS technology provides substantial advantages for large-scale integration,enabling the development of energy-efficient reservoir computing hardware.展开更多
β-Ga_(2)O_(3) MOS inverter should play a crucial role in β-Ga_(2)O_(3) electronic circuits. Enhancement-mode(E-mode) MOSFET was fabricated based on β-Ga_(2)O_(3) film grown by atomic layer deposition technology, an...β-Ga_(2)O_(3) MOS inverter should play a crucial role in β-Ga_(2)O_(3) electronic circuits. Enhancement-mode(E-mode) MOSFET was fabricated based on β-Ga_(2)O_(3) film grown by atomic layer deposition technology, and the β-Ga_(2)O_(3) inverter was further monolithically integrated on this basis. The β-Ga_(2)O_(3) n MOSFET exhibits excellent electrical characteristics with an on/off current ratio reaching 10^(5). The logic inverter shows outstanding voltage inversion characteristics under low-frequency from 1 to 400 Hz operation. As the frequency continues to increase to 10 K, the reverse characteristic becomes worse due to parasitic capacitance induced by processes, and the difference between the highest and lowest values of VOUT has an exponential decay relationship with the frequency. This paper provides the practice for the development of β-Ga_(2)O_(3)-based circuits.展开更多
This study focuses on a 60 V trench MOSFET device designed for operation in space radiation environments.By increasing the bulk region concentration and placing the etched gate trench after the P+implantation process,...This study focuses on a 60 V trench MOSFET device designed for operation in space radiation environments.By increasing the bulk region concentration and placing the etched gate trench after the P+implantation process,we successfully reduced the threshold voltage shift from 6.5 to 2.2 V under a total dose of 400 krad(Si)^(60)Co,allowing the device to operate normally.Structurally,by embedding the source metal in the active and terminal regions,the device demonstrated current degradation without experiencing single-event burnout when subjected to a drain voltage of 60 V and a linear energy transfer value of 75.4 MeV·cm^(2)∕mg from tantalum-ion incidence.TCAD simulations verified that the embedded source metal effectively suppressed parasitic transistor conduction and eliminated the base-region expansion effect,thereby lowering the maximum temperature from 8000 to 1400 K.The irradiation effects of the embedded source metal in the terminal region were also investigated,which can improve the reverse recovery and ensure that the terminal metal does not melt prematurely,thereby significantly enhancing the radiation hardness of the device.展开更多
The failure mechanisms and structural damage of SiC MOSFETs induced by heavy ion irradiation were demonstrated.The findings reveal three degradation modes,depending on the drain voltage.At a relatively low voltage,the...The failure mechanisms and structural damage of SiC MOSFETs induced by heavy ion irradiation were demonstrated.The findings reveal three degradation modes,depending on the drain voltage.At a relatively low voltage,the damage is triggered by the formation and activation of gate latent damage(LDs),with damage concentrated in the gate oxide.The second degradation mode involves permanent leakage current degradation,with damage progressively transitioning from the oxide to the SiC material as the drain voltage escalates.Ultimately,the device undergoes catastrophic burnout above certain voltages,characterized by the lattice temperature reaching the sublimation point of SiC,resulting in surface cavity and complete structural destruction.This paper presents a comprehensive investigation of SiC MOSFETs under heavy ion exposure,providing radiation resistance methods of SiC-based devices for aerospace applications.展开更多
为解决碳化硅金属氧化物半导体场效应晶体管(SiC Metal Oxide Semiconductor Field Effect Transistor,SiC MOSFET)硬开关故障(Hard Switch Fault,HSF)、负载故障(Fault Under Load,FUL)和过载故障(OverLoad fault,OL)的问题,本文提出...为解决碳化硅金属氧化物半导体场效应晶体管(SiC Metal Oxide Semiconductor Field Effect Transistor,SiC MOSFET)硬开关故障(Hard Switch Fault,HSF)、负载故障(Fault Under Load,FUL)和过载故障(OverLoad fault,OL)的问题,本文提出了一种基于SiC MOSFET漏极电压和源极电压检测的过流保护方法(OverCurrent Protection method based on the Drain-voltage and Source-voltage Detection,DSD-OCP).该方法通过检测电路实时监控SiC MOSFET的漏极电压和源极电压来准确识别短路故障和过载故障,并利用驱动电路控制SiC MOSFET的开通和关断,从而实现快速短路保护和自适应过载保护,同时还集成软关断功能.基于0.5μm双极型-互补金属氧化物半导体-双扩散金属氧化物半导体(Bipolar-CMOS-DMOS,BCD)工艺,设计了DSD-OCP电路并进行流片,芯片面积为2.8 mm^(2).采用研制的芯片搭建1200 V/80 mΩSiC MOSFET测试平台,并验证了DSD-OCP方法的有效性.实验结果表明,SiC MOSFET在DSD-OCP芯片保护下的HSF和FUL持续时间分别为88 ns和105 ns.在不同母线电压下,DSD-OCP芯片能够为SiC MOSFET提供自适应的过载保护.因DSD-OCP芯片具有软关断功能,SiC MOSFET在过流保护时的漏极电压过冲不超过110 V.展开更多
基金National Key Research and Development Program of China(2023YFA1609000)National Natural Science Foundation of China(62474190,U22B2043,U2267210)。
文摘The single-event susceptibility of three silicon carbide(SiC)metal-oxide-semiconductor field-effect transistor(MOSFET)power devices structures(planar,trench and double trench)is researched by the technology computer-aided design(TCAD)simulation.Comparative analysis of the heavy-ion irradiation effects on three device structures reveals distinct susceptibility characteristics.The gate oxide region is identified as the most sensitive position in planar devices,while trench and doubletrench structures exhibit no localized sensitive regions.Furthermore,the single-event susceptibility demonstrates strong depth dependence across all three structures,with enhanced vulnerability observed at greater ion penetration depths.
基金supported in part by the Chinese Academy of Sciences(No.XDA0330302)NSFC program(No.22127901)。
文摘Neuromorphic devices have garnered significant attention as potential building blocks for energy-efficient hardware systems owing to their capacity to emulate the computational efficiency of the brain.In this regard,reservoir computing(RC)framework,which leverages straightforward training methods and efficient temporal signal processing,has emerged as a promising scheme.While various physical reservoir devices,including ferroelectric,optoelectronic,and memristor-based systems,have been demonstrated,many still face challenges related to compatibility with mainstream complementary metal oxide semiconductor(CMOS)integration processes.This study introduced a silicon-based schottky barrier metal-oxide-semiconductor field effect transistor(SB-MOSFET),which was fabricated under low thermal budget and compatible with back-end-of-line(BEOL).The device demonstrated short-term memory characteristics,facilitated by the modulation of schottky barriers and charge trapping.Utilizing these characteristics,a RC system for temporal data processing was constructed,and its performance was validated in a 5×4 digital classification task,achieving an accuracy exceeding 98%after 50 training epochs.Furthermore,the system successfully processed temporal signal in waveform classification and prediction tasks using time-division multiplexing.Overall,the SB-MOSFET's high compatibility with CMOS technology provides substantial advantages for large-scale integration,enabling the development of energy-efficient reservoir computing hardware.
基金supported by Natural Science Basic Research Program of Shaanxi Province of China (No. 2023-JC-YB-574)National Natural Science Foundation of China (No. 62304178)。
文摘β-Ga_(2)O_(3) MOS inverter should play a crucial role in β-Ga_(2)O_(3) electronic circuits. Enhancement-mode(E-mode) MOSFET was fabricated based on β-Ga_(2)O_(3) film grown by atomic layer deposition technology, and the β-Ga_(2)O_(3) inverter was further monolithically integrated on this basis. The β-Ga_(2)O_(3) n MOSFET exhibits excellent electrical characteristics with an on/off current ratio reaching 10^(5). The logic inverter shows outstanding voltage inversion characteristics under low-frequency from 1 to 400 Hz operation. As the frequency continues to increase to 10 K, the reverse characteristic becomes worse due to parasitic capacitance induced by processes, and the difference between the highest and lowest values of VOUT has an exponential decay relationship with the frequency. This paper provides the practice for the development of β-Ga_(2)O_(3)-based circuits.
基金supported in part by National R&D Program for Major Research Instruments of China(No.62027814)。
文摘This study focuses on a 60 V trench MOSFET device designed for operation in space radiation environments.By increasing the bulk region concentration and placing the etched gate trench after the P+implantation process,we successfully reduced the threshold voltage shift from 6.5 to 2.2 V under a total dose of 400 krad(Si)^(60)Co,allowing the device to operate normally.Structurally,by embedding the source metal in the active and terminal regions,the device demonstrated current degradation without experiencing single-event burnout when subjected to a drain voltage of 60 V and a linear energy transfer value of 75.4 MeV·cm^(2)∕mg from tantalum-ion incidence.TCAD simulations verified that the embedded source metal effectively suppressed parasitic transistor conduction and eliminated the base-region expansion effect,thereby lowering the maximum temperature from 8000 to 1400 K.The irradiation effects of the embedded source metal in the terminal region were also investigated,which can improve the reverse recovery and ensure that the terminal metal does not melt prematurely,thereby significantly enhancing the radiation hardness of the device.
基金Project supported by the National Key Research and Development Program of China(Grant No.2023YFA1609000)the National Natural Science Foundation of China(Grant Nos.U2341222,U2441248,12275061,and 12075069)。
文摘The failure mechanisms and structural damage of SiC MOSFETs induced by heavy ion irradiation were demonstrated.The findings reveal three degradation modes,depending on the drain voltage.At a relatively low voltage,the damage is triggered by the formation and activation of gate latent damage(LDs),with damage concentrated in the gate oxide.The second degradation mode involves permanent leakage current degradation,with damage progressively transitioning from the oxide to the SiC material as the drain voltage escalates.Ultimately,the device undergoes catastrophic burnout above certain voltages,characterized by the lattice temperature reaching the sublimation point of SiC,resulting in surface cavity and complete structural destruction.This paper presents a comprehensive investigation of SiC MOSFETs under heavy ion exposure,providing radiation resistance methods of SiC-based devices for aerospace applications.
文摘为解决碳化硅金属氧化物半导体场效应晶体管(SiC Metal Oxide Semiconductor Field Effect Transistor,SiC MOSFET)硬开关故障(Hard Switch Fault,HSF)、负载故障(Fault Under Load,FUL)和过载故障(OverLoad fault,OL)的问题,本文提出了一种基于SiC MOSFET漏极电压和源极电压检测的过流保护方法(OverCurrent Protection method based on the Drain-voltage and Source-voltage Detection,DSD-OCP).该方法通过检测电路实时监控SiC MOSFET的漏极电压和源极电压来准确识别短路故障和过载故障,并利用驱动电路控制SiC MOSFET的开通和关断,从而实现快速短路保护和自适应过载保护,同时还集成软关断功能.基于0.5μm双极型-互补金属氧化物半导体-双扩散金属氧化物半导体(Bipolar-CMOS-DMOS,BCD)工艺,设计了DSD-OCP电路并进行流片,芯片面积为2.8 mm^(2).采用研制的芯片搭建1200 V/80 mΩSiC MOSFET测试平台,并验证了DSD-OCP方法的有效性.实验结果表明,SiC MOSFET在DSD-OCP芯片保护下的HSF和FUL持续时间分别为88 ns和105 ns.在不同母线电压下,DSD-OCP芯片能够为SiC MOSFET提供自适应的过载保护.因DSD-OCP芯片具有软关断功能,SiC MOSFET在过流保护时的漏极电压过冲不超过110 V.
