A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ...A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ections,yielding the gate bias dependent parameters,such as effective channel le ngth,parasitic resistance,and mobility,etc.This method avoids the gate bias rang e optimization,and retains the accuracy and simplicity of linear regression.The extracted gate bias dependent parameters are implemented in the compact I-V model which has been proposed for deep submicron LDD MOSFET's.The good agreemen ts between simulations and measurements of the devices on 0.18μm CMOS technolo gy indicate the effectivity of this technique.展开更多
A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good ...A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good agreement with measurement,and show that deep submicron LDD MOSFET has larger substrate current than submicron device does.The improved model costs low computation consumption,and is effective in manifestation of hot carrier effect and other effects in deep submicron devices,in turn is suitable for design and reliability analysis of scaling down devices.展开更多
A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channe...A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channel length and bias int o account.This is due to that the characteristics lenth significantly affects th e maximum lateral electric field and the length of velocity saturation region,bo th of which are very important in modeling the drain current and the substrate c urrent.The comparison between simulations and experiments shows a good predictio n of the model for submicron and deep-submicron LDD MOSFET.Moreover,the analyti cal model is suitable for descgn of devices as it is low in computation consumpt ion.展开更多
In order to study the abnormal substrate current and reliability problem of LDDMOSFET observed in experiments, two dimensional numerical simulation for devices has been performed, and an optimum process for LDD is sug...In order to study the abnormal substrate current and reliability problem of LDDMOSFET observed in experiments, two dimensional numerical simulation for devices has been performed, and an optimum process for LDD is suggested.展开更多
A new improved technique,based on the direct current current voltage and charge pumping methods,is proposed for measurements of interface traps density in the channel and the drain region for LDD n MOSFET.This tech...A new improved technique,based on the direct current current voltage and charge pumping methods,is proposed for measurements of interface traps density in the channel and the drain region for LDD n MOSFET.This technique can be applied to virgin samples and those subjected to hot carrier stress,and the latter are known to cause the interface damage in the drain region and the channel region.The generation of interface traps density in the channel region and in the drain region can be clearly distinguished by using this technique.展开更多
文摘A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ections,yielding the gate bias dependent parameters,such as effective channel le ngth,parasitic resistance,and mobility,etc.This method avoids the gate bias rang e optimization,and retains the accuracy and simplicity of linear regression.The extracted gate bias dependent parameters are implemented in the compact I-V model which has been proposed for deep submicron LDD MOSFET's.The good agreemen ts between simulations and measurements of the devices on 0.18μm CMOS technolo gy indicate the effectivity of this technique.
文摘A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good agreement with measurement,and show that deep submicron LDD MOSFET has larger substrate current than submicron device does.The improved model costs low computation consumption,and is effective in manifestation of hot carrier effect and other effects in deep submicron devices,in turn is suitable for design and reliability analysis of scaling down devices.
文摘A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channel length and bias int o account.This is due to that the characteristics lenth significantly affects th e maximum lateral electric field and the length of velocity saturation region,bo th of which are very important in modeling the drain current and the substrate c urrent.The comparison between simulations and experiments shows a good predictio n of the model for submicron and deep-submicron LDD MOSFET.Moreover,the analyti cal model is suitable for descgn of devices as it is low in computation consumpt ion.
文摘In order to study the abnormal substrate current and reliability problem of LDDMOSFET observed in experiments, two dimensional numerical simulation for devices has been performed, and an optimum process for LDD is suggested.
文摘A new improved technique,based on the direct current current voltage and charge pumping methods,is proposed for measurements of interface traps density in the channel and the drain region for LDD n MOSFET.This technique can be applied to virgin samples and those subjected to hot carrier stress,and the latter are known to cause the interface damage in the drain region and the channel region.The generation of interface traps density in the channel region and in the drain region can be clearly distinguished by using this technique.
