With sustaining change of production mode,layout planning is no longer a thing built once for all.Cellular layout(CL) is becoming a hotspot in the research field of manufacturing system layout.Traditional researches o...With sustaining change of production mode,layout planning is no longer a thing built once for all.Cellular layout(CL) is becoming a hotspot in the research field of manufacturing system layout.Traditional researches on layout planning are mainly concentrating on aspects of layout arithmetic,style and evaluation,etc.Relatively seldom efforts are paid to CL and its specific problems as cell formation(CF),equipment sharing and CL analysis.Through problem analyzing of layout in cellular manufacturing system(CMS),research approach of cell formation,interactive layout and layout analysis threaded with process interconnection relationship(PIR) is proposed.Typical key technologies in CL like CF technology based on similarity analysis of part processes,interactive visual layout technology,layout evaluation technology founded on PIR analysis and algorithm of cell equipment sharing are put forward.Against the background of one enterprise which encounters problems of low utility of key equipments and disperse material logistic,an example of four-cell layout is given.The CL adjustment and analysis results show that equipment with high level of sharing degree should be disposed around the boundary of its main cell,and be near to other sharing cells as possible; process route should be centralized by all means,so equipment adjustment is to be implemented along direction that route intersection can be decreased; giving consideration to the existence of discrete cell,logistic route and its density should be centralized to cells formed.The proposed research can help improve equipment utility and material logistic efficiency of CL,and can be popularized to other application availably.展开更多
As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polyn...As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.展开更多
As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree ...As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given t^uctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.展开更多
Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect r...Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs’ interconnect reliability and help the new entrants to understand the present situation of this area.展开更多
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.展开更多
Despite of good performance immunity to stress and high transmitting/receiving sensitivity advantages,the fabrication imperfection induced asynchronous vibration and the resultant prolonged ring-down tail severely lim...Despite of good performance immunity to stress and high transmitting/receiving sensitivity advantages,the fabrication imperfection induced asynchronous vibration and the resultant prolonged ring-down tail severely limit the potential of the cantilever beam-based piezoelectric micromachined ultrasonic transducer(PMUT)in pulse-echo applications as transceiver.To address this issue,a novel post processing soft interconnecting strategy is presented.In this case,specific reservoir structure is intentionally integrated into the cantilever-beam based PMUT design,under the assistance of which the liquid PDMS can be accurately applied and spontaneously driven to seal the air gaps between the already released cantilever beams via the capillary effect.After curing,the PDMS will be transformed from liquid to solid and serve as soft interconnecting spring between adjacent cantilever beams so as to force them to vibrate in synchronous mode.At the same time,this treatment does not change the existing fabrication process and has little effect on the original PMUT performance.From both of the mechanical and acoustic response measurement results,effective suppression for the asynchronous vibration and significant reduction of the ring-down tail have been successfully demonstrated for the treated PMUT device.In the subsequent pulse-echo rangefinding experiment,a distance detection range covering from 270.8 mm to 3.8 m with a divergence angle close to 170°has been achieved when it is driven at resonant frequency of 69.2 kHz with 40 Vpp,40-cycles sinusoidal signal.Given the simple yet effective treatment,the proposed strategy shows great prospective in developing high performance PMUT for in-air rangefinding applications.展开更多
基金supported by Defence Advanced Research Program of ChinaFoundation Research Program of Beijing Institute of Technology,China (Grant No. 20080342003)
文摘With sustaining change of production mode,layout planning is no longer a thing built once for all.Cellular layout(CL) is becoming a hotspot in the research field of manufacturing system layout.Traditional researches on layout planning are mainly concentrating on aspects of layout arithmetic,style and evaluation,etc.Relatively seldom efforts are paid to CL and its specific problems as cell formation(CF),equipment sharing and CL analysis.Through problem analyzing of layout in cellular manufacturing system(CMS),research approach of cell formation,interactive layout and layout analysis threaded with process interconnection relationship(PIR) is proposed.Typical key technologies in CL like CF technology based on similarity analysis of part processes,interactive visual layout technology,layout evaluation technology founded on PIR analysis and algorithm of cell equipment sharing are put forward.Against the background of one enterprise which encounters problems of low utility of key equipments and disperse material logistic,an example of four-cell layout is given.The CL adjustment and analysis results show that equipment with high level of sharing degree should be disposed around the boundary of its main cell,and be near to other sharing cells as possible; process route should be centralized by all means,so equipment adjustment is to be implemented along direction that route intersection can be decreased; giving consideration to the existence of discrete cell,logistic route and its density should be centralized to cells formed.The proposed research can help improve equipment utility and material logistic efficiency of CL,and can be popularized to other application availably.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60725415 and 60971066)the National Science&Technology Important Project of China(Grant No.2009ZX01034-002-001-005)The National Key Laboratory Foundation(Grant No.ZHD200904)
文摘As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60606006)the National Science Fund forDistinguished Young Scholars of China (Grant No. 60725415)the Basic Science Research Fund in Xidian University,China
文摘As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given t^uctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.
文摘Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs’ interconnect reliability and help the new entrants to understand the present situation of this area.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation,China (Grant No. ZHD200904)
文摘On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.
文摘随着市场对生产制造的柔性及产品质量要求的提高,生产操作人员需要在短时间内了解设备的电气互联流程及各线束在系统的分布情况。文章通过分析光电设备电气互联工艺的问题及原因,提出光电设备电气互联工艺可视化设计思路,并应用Visual Studio 2015 C++作为编程工具、My SQL作为数据库,结合Qt图形用户界面应用程序,实现对光电设备电气互联工艺的可视化设计,从而提高生产操作人员的工作效率以及产品质量。
基金supported by the National Natural Science Foundation of China(NSFC)(12174137)Innovation Project of Optics Valley Laboratory(Grant No.OVL2023ZD003).
文摘Despite of good performance immunity to stress and high transmitting/receiving sensitivity advantages,the fabrication imperfection induced asynchronous vibration and the resultant prolonged ring-down tail severely limit the potential of the cantilever beam-based piezoelectric micromachined ultrasonic transducer(PMUT)in pulse-echo applications as transceiver.To address this issue,a novel post processing soft interconnecting strategy is presented.In this case,specific reservoir structure is intentionally integrated into the cantilever-beam based PMUT design,under the assistance of which the liquid PDMS can be accurately applied and spontaneously driven to seal the air gaps between the already released cantilever beams via the capillary effect.After curing,the PDMS will be transformed from liquid to solid and serve as soft interconnecting spring between adjacent cantilever beams so as to force them to vibrate in synchronous mode.At the same time,this treatment does not change the existing fabrication process and has little effect on the original PMUT performance.From both of the mechanical and acoustic response measurement results,effective suppression for the asynchronous vibration and significant reduction of the ring-down tail have been successfully demonstrated for the treated PMUT device.In the subsequent pulse-echo rangefinding experiment,a distance detection range covering from 270.8 mm to 3.8 m with a divergence angle close to 170°has been achieved when it is driven at resonant frequency of 69.2 kHz with 40 Vpp,40-cycles sinusoidal signal.Given the simple yet effective treatment,the proposed strategy shows great prospective in developing high performance PMUT for in-air rangefinding applications.
