Traditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters(ADC).However,the cost and power consumption of an entire electronic readout system based on digitizers fo...Traditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters(ADC).However,the cost and power consumption of an entire electronic readout system based on digitizers for a PET scanner are high.To address this problem,a soft-core ADC based on a field-programmable gate array(FPGA)was proposed.An FPGA-based ADC(FPGA-ADC)combines low loss and high performance.To achieve good performance,the FPGA-ADC requires three calibrations:time-to-digital converter(TDC)length calibration,TDC alignment calibration,and TDC-to-ADC calibration.A prototype front-end electronics based on FPGA-ADC was built to evaluate the performance of time-of-flight positron emission tomography(TOF PET)detectors.Each PET detector consists of a LYSO crystal single-ended coupled to a silicon photomultiplier(SiPM).The experimental results show that the full-width at half-maximum(FWHM)energy resolution for 511 keV gamma photons after saturation correction of the SiPM was 12.3%.The FWHM coincidence timing resolution(CTR)of the TOF PET detector with the readout of the front-end electronic prototype is 385.2 ps.FPGA-ADCbased front-end electronics are very promising for multichannel,low-cost,highly integrated,and power-efficient readout electronic systems for radiation detector applications.展开更多
红外焦平面探测器输出的模拟信号通常采用14 bit AD进行数字化,并进行后续处理,而常用的显示设备只能显示8 bit图像,于是最终显示需要对图像进行压缩,压缩过程直接影响显示效果。与之相关的图像细节增强和动态范围压缩技术亦是当前行业...红外焦平面探测器输出的模拟信号通常采用14 bit AD进行数字化,并进行后续处理,而常用的显示设备只能显示8 bit图像,于是最终显示需要对图像进行压缩,压缩过程直接影响显示效果。与之相关的图像细节增强和动态范围压缩技术亦是当前行业内重点研究的技术。基于已提出的一种细节增强和动态压缩算法,在以Xilinx公司的XC5VLX50T FPGA为核心处理器件的图像处理板上对算法进行了工程实现,算法完全在FPGA片内利用Verilog-HDL编写实现,不占用片外资源,片内占用资源适中,处理延时小于200μs。实际观测试验验证了算法以及实现手段的有效性。展开更多
基金supported by the Key R&D Program of Shandong Province(No.2023SFGC0101)Shandong Excellent Young Scientists Fund Program(Overseas)(No.2023HWYQ-047)+1 种基金the Natural Science Foundation of Shandong Province(No.ZR2022QA039)the National Natural Science Foundation of China(NSFC)(No.U2106202).
文摘Traditional digitizers for signal readout of PET detectors are based on commercial analog-to-digital converters(ADC).However,the cost and power consumption of an entire electronic readout system based on digitizers for a PET scanner are high.To address this problem,a soft-core ADC based on a field-programmable gate array(FPGA)was proposed.An FPGA-based ADC(FPGA-ADC)combines low loss and high performance.To achieve good performance,the FPGA-ADC requires three calibrations:time-to-digital converter(TDC)length calibration,TDC alignment calibration,and TDC-to-ADC calibration.A prototype front-end electronics based on FPGA-ADC was built to evaluate the performance of time-of-flight positron emission tomography(TOF PET)detectors.Each PET detector consists of a LYSO crystal single-ended coupled to a silicon photomultiplier(SiPM).The experimental results show that the full-width at half-maximum(FWHM)energy resolution for 511 keV gamma photons after saturation correction of the SiPM was 12.3%.The FWHM coincidence timing resolution(CTR)of the TOF PET detector with the readout of the front-end electronic prototype is 385.2 ps.FPGA-ADCbased front-end electronics are very promising for multichannel,low-cost,highly integrated,and power-efficient readout electronic systems for radiation detector applications.
文摘红外焦平面探测器输出的模拟信号通常采用14 bit AD进行数字化,并进行后续处理,而常用的显示设备只能显示8 bit图像,于是最终显示需要对图像进行压缩,压缩过程直接影响显示效果。与之相关的图像细节增强和动态范围压缩技术亦是当前行业内重点研究的技术。基于已提出的一种细节增强和动态压缩算法,在以Xilinx公司的XC5VLX50T FPGA为核心处理器件的图像处理板上对算法进行了工程实现,算法完全在FPGA片内利用Verilog-HDL编写实现,不占用片外资源,片内占用资源适中,处理延时小于200μs。实际观测试验验证了算法以及实现手段的有效性。
